evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mmc: sdhci-msm: adapt to allow drop-in use in place of downstream driver

Browse source 
In order for this driver to function as a drop-in replacement for the
msm-3.10 driver:

  - Allow selectability on ARCH_MSM
  - Rename clock names to include _clk prefix
  - Change supported compatible string

Change-Id: I20bc683512ebdd22fcd7845c7e43dd645a2f146f
Signed-off-by: Georgi Djakov <gdjako@codeaurora.org>
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
[venkatg@codeaurora.org: fix kconfig options conflict]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
This commit is contained in:
Georgi Djakov 2014-07-31 16:40:32 +03:00 • committed by Subhash Jadavani
parent 7cc9ec9f2a
commit d51a3603b4
2 changed files with 13 additions and 5 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
drivers/mmc/host/Kconfig
View file

@ -406,7 +406,7 @@ config MMC_ATMELMCI
config MMC_SDHCI_MSM
tristate "Qualcomm SDHCI Controller Support"
depends on ARCH_QCOM || (ARM && COMPILE_TEST)
depends on ARCH_QCOM || ARCH_MSM || (ARM && COMPILE_TEST)
depends on MMC_SDHCI_PLTFM
help
This selects the Secure Digital Host Controller Interface (SDHCI)

16
drivers/mmc/host/sdhci-msm.c
View file

@ -31,6 +31,8 @@
#define HC_MODE_EN 0x1
#define CORE_POWER 0x0
#define CORE_SW_RST BIT(7)
#define CORE_HC_SELECT_IN_EN (1 << 18)
#define CORE_HC_SELECT_IN_MASK (7 << 19)
#define MAX_PHASES 16
#define CORE_DLL_LOCK BIT(7)
@ -412,7 +414,7 @@ retry:
}
static const struct of_device_id sdhci_msm_dt_match[] = {
{ .compatible = "qcom,sdhci-msm-v4" },
{ .compatible = "qcom,sdhci-msm" },
{},
};
@ -458,7 +460,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
sdhci_get_of_property(pdev);
/* Setup SDCC bus voter clock. */
msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
if (!IS_ERR(msm_host->bus_clk)) {
/* Vote for max. clk rate for max. performance */
ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
@ -470,7 +472,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
}
/* Setup main peripheral bus clock */
msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
msm_host->pclk = devm_clk_get(&pdev->dev, "iface_clk");
if (IS_ERR(msm_host->pclk)) {
ret = PTR_ERR(msm_host->pclk);
dev_err(&pdev->dev, "Perpheral clk setup failed (%d)\n", ret);
@ -482,7 +484,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)
goto bus_clk_disable;
/* Setup SDC MMC clock */
msm_host->clk = devm_clk_get(&pdev->dev, "core");
msm_host->clk = devm_clk_get(&pdev->dev, "core_clk");
if (IS_ERR(msm_host->clk)) {
ret = PTR_ERR(msm_host->clk);
dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
@ -507,6 +509,12 @@ static int sdhci_msm_probe(struct platform_device *pdev)
goto clk_disable;
}
/* Disable mode selection via the vendor specific register */
writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
& ~CORE_HC_SELECT_IN_EN
& ~CORE_HC_SELECT_IN_MASK),
host->ioaddr + CORE_VENDOR_SPEC);
/* Reset the core and Enable SDHC mode */
writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) |
CORE_SW_RST, msm_host->core_mem + CORE_POWER);