Merge "qpnp-fg-gen3: Add support to configure force battery profile loading"
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5 changed files with 207 additions and 82 deletions
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@ -87,7 +87,8 @@ First Level Node - FG Gen3 device
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Value type: <u32>
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Definition: Percentage of monotonic SOC increase upon which the delta
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SOC interrupt will be triggered. If this property is not
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specified, then the default value will be 1.
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specified, then the default value will be 1. Possible
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values are in the range of 0 to 12.
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- qcom,fg-recharge-soc-thr
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Usage: optional
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@ -145,6 +146,13 @@ First Level Node - FG Gen3 device
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Value type: <bool>
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Definition: Enables the cycle counter feature.
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- qcom,fg-force-load-profile
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Usage: optional
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Value type: <bool>
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Definition: If set, battery profile will be force loaded if the profile
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loaded earlier by bootloader doesn't match with the profile
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available in the device tree.
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==========================================================
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Second Level Nodes - Peripherals managed by FG Gen3 driver
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==========================================================
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@ -13,6 +13,7 @@
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qcom,ascent_3450mah {
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/* #Ascent_860_82209_0000_3450mAh_averaged_MasterSlave_Jul20th2016*/
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qcom,max-voltage-uv = <4350000>;
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qcom,fg-cc-cv-threshold-mv = <4340>;
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qcom,nom-batt-capacity-mah = <3450>;
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qcom,batt-id-kohm = <60>;
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qcom,battery-beta = <3435>;
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@ -13,6 +13,7 @@
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qcom,itech_3000mah {
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/* #Itech_B00826LF_3000mAh_ver1660_averaged_MasterSlave_Jul20th2016*/
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qcom,max-voltage-uv = <4350000>;
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qcom,fg-cc-cv-threshold-mv = <4340>;
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qcom,nom-batt-capacity-mah = <3000>;
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qcom,batt-id-kohm = <100>;
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qcom,battery-beta = <3450>;
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@ -54,6 +54,8 @@
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CHARS_PER_ITEM) + 1) \
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#define FG_SRAM_ADDRESS_MAX 255
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#define PROFILE_LEN 224
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#define PROFILE_COMP_LEN 148
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#define BUCKET_COUNT 8
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#define BUCKET_SOC_PCT (256 / BUCKET_COUNT)
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@ -121,6 +123,8 @@ enum fg_sram_param_id {
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FG_SRAM_CUTOFF_VOLT,
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FG_SRAM_EMPTY_VOLT,
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FG_SRAM_VBATT_LOW,
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FG_SRAM_FLOAT_VOLT,
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FG_SRAM_VBATT_FULL,
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FG_SRAM_ESR_TIMER_DISCHG_MAX,
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FG_SRAM_ESR_TIMER_DISCHG_INIT,
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FG_SRAM_ESR_TIMER_CHG_MAX,
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@ -177,6 +181,7 @@ struct fg_dt_props {
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int esr_timer_charging;
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int esr_timer_awake;
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int esr_timer_asleep;
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bool force_load_profile;
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};
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/* parameters from battery profile */
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@ -184,6 +189,7 @@ struct fg_batt_props {
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const char *batt_type_str;
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char *batt_profile;
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int float_volt_uv;
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int vbatt_full_mv;
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int fastchg_curr_ma;
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int batt_id_kohm;
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};
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@ -200,8 +206,8 @@ struct fg_cyc_ctr_data {
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struct fg_irq_info {
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const char *name;
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const irq_handler_t handler;
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int irq;
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bool wakeable;
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int irq;
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};
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struct fg_chip {
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@ -217,7 +223,7 @@ struct fg_chip {
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struct votable *awake_votable;
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struct fg_sram_param *sp;
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int *debug_mask;
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char *batt_profile;
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char batt_profile[PROFILE_LEN];
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struct fg_dt_props dt;
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struct fg_batt_props bp;
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struct fg_cyc_ctr_data cyc_ctr;
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@ -227,10 +233,11 @@ struct fg_chip {
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u32 batt_soc_base;
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u32 batt_info_base;
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u32 mem_if_base;
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int batt_id;
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int nom_cap_uah;
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int status;
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int prev_status;
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bool batt_id_avail;
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bool profile_available;
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bool profile_loaded;
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bool battery_missing;
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struct completion soc_update;
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@ -35,6 +35,8 @@
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#define CUTOFF_VOLT_OFFSET 0
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#define SYS_TERM_CURR_WORD 6
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#define SYS_TERM_CURR_OFFSET 0
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#define VBATT_FULL_WORD 7
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#define VBATT_FULL_OFFSET 0
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#define DELTA_SOC_THR_WORD 12
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#define DELTA_SOC_THR_OFFSET 3
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#define RECHARGE_SOC_THR_WORD 14
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@ -89,6 +91,8 @@
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#define EMPTY_VOLT_v2_OFFSET 3
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#define VBATT_LOW_v2_WORD 16
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#define VBATT_LOW_v2_OFFSET 0
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#define FLOAT_VOLT_v2_WORD 16
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#define FLOAT_VOLT_v2_OFFSET 2
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static int fg_decode_value_16b(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val);
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@ -97,9 +101,9 @@ static int fg_decode_default(struct fg_sram_param *sp,
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static int fg_decode_batt_soc(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val);
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static void fg_encode_voltage(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val, u8 *buf);
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enum fg_sram_param_id id, int val_mv, u8 *buf);
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static void fg_encode_current(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val, u8 *buf);
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enum fg_sram_param_id id, int val_ma, u8 *buf);
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static void fg_encode_default(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val, u8 *buf);
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@ -134,11 +138,13 @@ static struct fg_sram_param pmicobalt_v1_sram_params[] = {
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-2500, fg_encode_voltage, NULL),
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PARAM(VBATT_LOW, VBATT_LOW_WORD, VBATT_LOW_OFFSET, 1, 100000, 390625,
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-2500, fg_encode_voltage, NULL),
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PARAM(VBATT_FULL, VBATT_FULL_WORD, VBATT_FULL_OFFSET, 2, 1000000,
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244141, 0, fg_encode_voltage, NULL),
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PARAM(SYS_TERM_CURR, SYS_TERM_CURR_WORD, SYS_TERM_CURR_OFFSET, 3,
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1000000, 122070, 0, fg_encode_current, NULL),
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PARAM(CHG_TERM_CURR, CHG_TERM_CURR_WORD, CHG_TERM_CURR_OFFSET, 1,
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100000, 390625, 0, fg_encode_current, NULL),
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PARAM(DELTA_SOC_THR, DELTA_SOC_THR_WORD, DELTA_SOC_THR_OFFSET, 1, 256,
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PARAM(DELTA_SOC_THR, DELTA_SOC_THR_WORD, DELTA_SOC_THR_OFFSET, 1, 2048,
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100, 0, fg_encode_default, NULL),
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PARAM(RECHARGE_SOC_THR, RECHARGE_SOC_THR_WORD, RECHARGE_SOC_THR_OFFSET,
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1, 256, 100, 0, fg_encode_default, NULL),
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@ -172,12 +178,16 @@ static struct fg_sram_param pmicobalt_v2_sram_params[] = {
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15625, -2000, fg_encode_voltage, NULL),
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PARAM(VBATT_LOW, VBATT_LOW_v2_WORD, VBATT_LOW_v2_OFFSET, 1, 1000,
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15625, -2000, fg_encode_voltage, NULL),
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PARAM(FLOAT_VOLT, FLOAT_VOLT_v2_WORD, FLOAT_VOLT_v2_OFFSET, 1, 1000,
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15625, -2000, fg_encode_voltage, NULL),
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PARAM(VBATT_FULL, VBATT_FULL_WORD, VBATT_FULL_OFFSET, 2, 1000000,
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244141, 0, fg_encode_voltage, NULL),
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PARAM(SYS_TERM_CURR, SYS_TERM_CURR_WORD, SYS_TERM_CURR_OFFSET, 3,
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1000000, 122070, 0, fg_encode_current, NULL),
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PARAM(CHG_TERM_CURR, CHG_TERM_CURR_v2_WORD, CHG_TERM_CURR_v2_OFFSET, 1,
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100000, 390625, 0, fg_encode_current, NULL),
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PARAM(DELTA_SOC_THR, DELTA_SOC_THR_v2_WORD, DELTA_SOC_THR_v2_OFFSET, 1,
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256, 100, 0, fg_encode_default, NULL),
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2048, 100, 0, fg_encode_default, NULL),
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PARAM(RECHARGE_SOC_THR, RECHARGE_SOC_THR_v2_WORD,
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RECHARGE_SOC_THR_v2_OFFSET, 1, 256, 100, 0, fg_encode_default,
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NULL),
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@ -264,6 +274,12 @@ module_param_named(
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sram_update_period_ms, fg_sram_update_period_ms, int, S_IRUSR | S_IWUSR
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);
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static bool fg_sram_dump;
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module_param_named(
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sram_dump, fg_sram_dump, bool, S_IRUSR | S_IWUSR
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);
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/* All getters HERE */
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static int fg_decode_value_16b(struct fg_sram_param *sp,
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@ -302,14 +318,14 @@ static int fg_decode(struct fg_sram_param *sp, enum fg_sram_param_id id,
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}
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static void fg_encode_voltage(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val, u8 *buf)
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enum fg_sram_param_id id, int val_mv, u8 *buf)
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{
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int i, mask = 0xff;
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int64_t temp;
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val += sp[id].offset;
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temp = (int64_t)div_u64((u64)val * sp[id].numrtr, sp[id].denmtr);
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pr_debug("temp: %llx id: %d, val: %d, buf: [ ", temp, id, val);
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val_mv += sp[id].offset;
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temp = (int64_t)div_u64((u64)val_mv * sp[id].numrtr, sp[id].denmtr);
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pr_debug("temp: %llx id: %d, val_mv: %d, buf: [ ", temp, id, val_mv);
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for (i = 0; i < sp[id].len; i++) {
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buf[i] = temp & mask;
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temp >>= 8;
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@ -319,15 +335,15 @@ static void fg_encode_voltage(struct fg_sram_param *sp,
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}
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static void fg_encode_current(struct fg_sram_param *sp,
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enum fg_sram_param_id id, int val, u8 *buf)
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enum fg_sram_param_id id, int val_ma, u8 *buf)
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{
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int i, mask = 0xff;
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int64_t temp;
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s64 current_ma;
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current_ma = val;
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current_ma = val_ma;
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temp = (int64_t)div_s64(current_ma * sp[id].numrtr, sp[id].denmtr);
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pr_debug("temp: %llx id: %d, val: %d, buf: [ ", temp, id, val);
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pr_debug("temp: %llx id: %d, val: %d, buf: [ ", temp, id, val_ma);
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for (i = 0; i < sp[id].len; i++) {
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buf[i] = temp & mask;
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temp >>= 8;
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@ -593,14 +609,12 @@ static int fg_get_batt_id(struct fg_chip *chip, int *val)
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return rc;
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}
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chip->batt_id_avail = true;
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fg_dbg(chip, FG_STATUS, "batt_id: %d\n", batt_id);
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*val = batt_id;
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return 0;
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}
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#define PROFILE_LEN 224
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static int fg_get_batt_profile(struct fg_chip *chip)
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{
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struct device_node *node = chip->dev->of_node;
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@ -614,13 +628,14 @@ static int fg_get_batt_profile(struct fg_chip *chip)
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return rc;
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}
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batt_id /= 1000;
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chip->batt_id = batt_id;
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batt_node = of_find_node_by_name(node, "qcom,battery-data");
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if (!batt_node) {
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pr_err("Batterydata not available\n");
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return -ENXIO;
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}
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batt_id /= 1000;
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profile_node = of_batterydata_get_best_profile(batt_node, batt_id,
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NULL);
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if (IS_ERR(profile_node))
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@ -652,6 +667,13 @@ static int fg_get_batt_profile(struct fg_chip *chip)
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chip->bp.fastchg_curr_ma = -EINVAL;
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}
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rc = of_property_read_u32(profile_node, "qcom,fg-cc-cv-threshold-mv",
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&chip->bp.vbatt_full_mv);
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if (rc < 0) {
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pr_err("battery cc_cv threshold unavailable, rc:%d\n", rc);
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chip->bp.vbatt_full_mv = -EINVAL;
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}
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data = of_get_property(profile_node, "qcom,fg-profile-data", &len);
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if (!data) {
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pr_err("No profile data available\n");
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@ -663,6 +685,7 @@ static int fg_get_batt_profile(struct fg_chip *chip)
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return -EINVAL;
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}
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chip->profile_available = true;
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memcpy(chip->batt_profile, data, len);
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return 0;
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}
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@ -912,46 +935,82 @@ static int fg_get_cycle_count(struct fg_chip *chip)
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return count;
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}
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#define PROFILE_COMP_LEN 32
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#define SOC_READY_WAIT_MS 2000
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static void profile_load_work(struct work_struct *work)
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static void dump_sram(u8 *buf, int len)
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{
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struct fg_chip *chip = container_of(work,
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struct fg_chip,
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profile_load_work.work);
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int rc;
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u8 buf[PROFILE_COMP_LEN], val;
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bool tried_again = false, profiles_same = false;
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int i;
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char str[16];
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if (!chip->batt_id_avail) {
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pr_err("batt_id not available\n");
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return;
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for (i = 0; i < len; i += 4) {
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str[0] = '\0';
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fill_string(str, sizeof(str), buf + i, 4);
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pr_info("%03d %s\n", PROFILE_LOAD_WORD + (i / 4), str);
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}
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}
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static bool is_profile_load_required(struct fg_chip *chip)
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{
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u8 buf[PROFILE_COMP_LEN], val;
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bool profiles_same = false;
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int rc;
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rc = fg_sram_read(chip, PROFILE_INTEGRITY_WORD,
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PROFILE_INTEGRITY_OFFSET, &val, 1, FG_IMA_DEFAULT);
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if (rc < 0) {
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pr_err("failed to read profile integrity rc=%d\n", rc);
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return;
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return false;
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}
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vote(chip->awake_votable, PROFILE_LOAD, true, 0);
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/* Check if integrity bit is set */
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if (val == 0x01) {
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fg_dbg(chip, FG_STATUS, "Battery profile integrity bit is set\n");
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rc = fg_sram_read(chip, PROFILE_LOAD_WORD, PROFILE_LOAD_OFFSET,
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buf, PROFILE_COMP_LEN, FG_IMA_DEFAULT);
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if (rc < 0) {
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pr_err("Error in reading battery profile, rc:%d\n", rc);
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goto out;
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return false;
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}
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profiles_same = memcmp(chip->batt_profile, buf,
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PROFILE_COMP_LEN) == 0;
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if (profiles_same) {
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fg_dbg(chip, FG_STATUS, "Battery profile is same\n");
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fg_dbg(chip, FG_STATUS, "Battery profile is same, not loading it\n");
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return false;
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}
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if (!chip->dt.force_load_profile) {
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pr_warn("Profiles doesn't match, skipping loading it since force_load_profile is disabled\n");
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if (fg_sram_dump) {
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pr_info("FG: loaded profile:\n");
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dump_sram(buf, PROFILE_COMP_LEN);
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pr_info("FG: available profile:\n");
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dump_sram(chip->batt_profile, PROFILE_LEN);
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}
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return false;
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}
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fg_dbg(chip, FG_STATUS, "Profiles are different, loading the correct one\n");
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} else {
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fg_dbg(chip, FG_STATUS, "Profile integrity bit is not set\n");
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if (fg_sram_dump) {
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pr_info("FG: profile to be loaded:\n");
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dump_sram(chip->batt_profile, PROFILE_LEN);
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}
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}
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return true;
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}
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#define SOC_READY_WAIT_MS 2000
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static void profile_load_work(struct work_struct *work)
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{
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struct fg_chip *chip = container_of(work,
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struct fg_chip,
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profile_load_work.work);
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bool tried_again = false;
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u8 buf[2], val;
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int rc;
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vote(chip->awake_votable, PROFILE_LOAD, true, 0);
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if (!is_profile_load_required(chip))
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goto done;
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}
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fg_dbg(chip, FG_STATUS, "profiles are different?\n");
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}
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clear_cycle_counter(chip);
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fg_dbg(chip, FG_STATUS, "profile loading started\n");
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@ -1182,6 +1241,32 @@ static int fg_hw_init(struct fg_chip *chip)
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return rc;
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}
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/* This SRAM register is only present in v2.0 */
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if (chip->pmic_rev_id->rev4 == PMICOBALT_V2P0_REV4 &&
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chip->bp.float_volt_uv > 0) {
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fg_encode(chip->sp, FG_SRAM_FLOAT_VOLT,
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chip->bp.float_volt_uv / 1000, buf);
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rc = fg_sram_write(chip, chip->sp[FG_SRAM_FLOAT_VOLT].addr_word,
|
||||
chip->sp[FG_SRAM_FLOAT_VOLT].addr_byte, buf,
|
||||
chip->sp[FG_SRAM_FLOAT_VOLT].len, FG_IMA_DEFAULT);
|
||||
if (rc < 0) {
|
||||
pr_err("Error in writing float_volt, rc=%d\n", rc);
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
|
||||
if (chip->bp.vbatt_full_mv > 0) {
|
||||
fg_encode(chip->sp, FG_SRAM_VBATT_FULL, chip->bp.vbatt_full_mv,
|
||||
buf);
|
||||
rc = fg_sram_write(chip, chip->sp[FG_SRAM_VBATT_FULL].addr_word,
|
||||
chip->sp[FG_SRAM_VBATT_FULL].addr_byte, buf,
|
||||
chip->sp[FG_SRAM_VBATT_FULL].len, FG_IMA_DEFAULT);
|
||||
if (rc < 0) {
|
||||
pr_err("Error in writing vbatt_full, rc=%d\n", rc);
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
|
||||
fg_encode(chip->sp, FG_SRAM_CHG_TERM_CURR, chip->dt.chg_term_curr_ma,
|
||||
buf);
|
||||
rc = fg_sram_write(chip, chip->sp[FG_SRAM_CHG_TERM_CURR].addr_word,
|
||||
|
|
@ -1311,28 +1396,6 @@ static int fg_memif_init(struct fg_chip *chip)
|
|||
return fg_ima_init(chip);
|
||||
}
|
||||
|
||||
static int fg_batt_profile_init(struct fg_chip *chip)
|
||||
{
|
||||
int rc;
|
||||
|
||||
if (!chip->batt_profile) {
|
||||
chip->batt_profile = devm_kcalloc(chip->dev, PROFILE_LEN,
|
||||
sizeof(*chip->batt_profile),
|
||||
GFP_KERNEL);
|
||||
if (!chip->batt_profile)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
rc = fg_get_batt_profile(chip);
|
||||
if (rc < 0) {
|
||||
pr_err("Error in getting battery profile, rc:%d\n", rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
schedule_delayed_work(&chip->profile_load_work, msecs_to_jiffies(0));
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* INTERRUPT HANDLERS STAY HERE */
|
||||
|
||||
static irqreturn_t fg_vbatt_low_irq_handler(int irq, void *data)
|
||||
|
|
@ -1360,16 +1423,16 @@ static irqreturn_t fg_batt_missing_irq_handler(int irq, void *data)
|
|||
chip->battery_missing = (status & BT_MISS_BIT);
|
||||
|
||||
if (chip->battery_missing) {
|
||||
chip->batt_id_avail = false;
|
||||
chip->profile_available = false;
|
||||
chip->profile_loaded = false;
|
||||
clear_cycle_counter(chip);
|
||||
} else {
|
||||
rc = fg_batt_profile_init(chip);
|
||||
rc = fg_get_batt_profile(chip);
|
||||
if (rc < 0) {
|
||||
pr_err("Error in initializing battery profile, rc=%d\n",
|
||||
rc);
|
||||
pr_err("Error in getting battery profile, rc:%d\n", rc);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
schedule_delayed_work(&chip->profile_load_work, 0);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
|
|
@ -1445,39 +1508,78 @@ static irqreturn_t fg_dummy_irq_handler(int irq, void *data)
|
|||
static struct fg_irq_info fg_irqs[FG_IRQ_MAX] = {
|
||||
/* BATT_SOC irqs */
|
||||
[MSOC_FULL_IRQ] = {
|
||||
"msoc-full", fg_soc_irq_handler, true },
|
||||
.name = "msoc-full",
|
||||
.handler = fg_soc_irq_handler,
|
||||
},
|
||||
[MSOC_HIGH_IRQ] = {
|
||||
"msoc-high", fg_soc_irq_handler, true },
|
||||
.name = "msoc-high",
|
||||
.handler = fg_soc_irq_handler,
|
||||
.wakeable = true,
|
||||
},
|
||||
[MSOC_EMPTY_IRQ] = {
|
||||
"msoc-empty", fg_empty_soc_irq_handler, true },
|
||||
.name = "msoc-empty",
|
||||
.handler = fg_empty_soc_irq_handler,
|
||||
.wakeable = true,
|
||||
},
|
||||
[MSOC_LOW_IRQ] = {
|
||||
"msoc-low", fg_soc_irq_handler },
|
||||
.name = "msoc-low",
|
||||
.handler = fg_soc_irq_handler,
|
||||
.wakeable = true,
|
||||
},
|
||||
[MSOC_DELTA_IRQ] = {
|
||||
"msoc-delta", fg_delta_soc_irq_handler, true },
|
||||
.name = "msoc-delta",
|
||||
.handler = fg_delta_soc_irq_handler,
|
||||
.wakeable = true,
|
||||
},
|
||||
[BSOC_DELTA_IRQ] = {
|
||||
"bsoc-delta", fg_delta_soc_irq_handler, true },
|
||||
.name = "bsoc-delta",
|
||||
.handler = fg_dummy_irq_handler,
|
||||
},
|
||||
[SOC_READY_IRQ] = {
|
||||
"soc-ready", fg_first_est_irq_handler, true },
|
||||
.name = "soc-ready",
|
||||
.handler = fg_first_est_irq_handler,
|
||||
.wakeable = true,
|
||||
},
|
||||
[SOC_UPDATE_IRQ] = {
|
||||
"soc-update", fg_soc_update_irq_handler },
|
||||
.name = "soc-update",
|
||||
.handler = fg_soc_update_irq_handler,
|
||||
},
|
||||
/* BATT_INFO irqs */
|
||||
[BATT_TEMP_DELTA_IRQ] = {
|
||||
"batt-temp-delta", fg_delta_batt_temp_irq_handler },
|
||||
.name = "batt-temp-delta",
|
||||
.handler = fg_delta_batt_temp_irq_handler,
|
||||
},
|
||||
[BATT_MISSING_IRQ] = {
|
||||
"batt-missing", fg_batt_missing_irq_handler, true },
|
||||
.name = "batt-missing",
|
||||
.handler = fg_batt_missing_irq_handler,
|
||||
.wakeable = true,
|
||||
},
|
||||
[ESR_DELTA_IRQ] = {
|
||||
"esr-delta", fg_dummy_irq_handler },
|
||||
.name = "esr-delta",
|
||||
.handler = fg_dummy_irq_handler,
|
||||
},
|
||||
[VBATT_LOW_IRQ] = {
|
||||
"vbatt-low", fg_vbatt_low_irq_handler, true },
|
||||
.name = "vbatt-low",
|
||||
.handler = fg_vbatt_low_irq_handler,
|
||||
.wakeable = true,
|
||||
},
|
||||
[VBATT_PRED_DELTA_IRQ] = {
|
||||
"vbatt-pred-delta", fg_dummy_irq_handler },
|
||||
.name = "vbatt-pred-delta",
|
||||
.handler = fg_dummy_irq_handler,
|
||||
},
|
||||
/* MEM_IF irqs */
|
||||
[DMA_GRANT_IRQ] = {
|
||||
"dma-grant", fg_dummy_irq_handler },
|
||||
.name = "dma-grant",
|
||||
.handler = fg_dummy_irq_handler,
|
||||
},
|
||||
[MEM_XCP_IRQ] = {
|
||||
"mem-xcp", fg_dummy_irq_handler },
|
||||
.name = "mem-xcp",
|
||||
.handler = fg_dummy_irq_handler,
|
||||
},
|
||||
[IMA_RDY_IRQ] = {
|
||||
"ima-rdy", fg_dummy_irq_handler },
|
||||
.name = "ima-rdy",
|
||||
.handler = fg_dummy_irq_handler,
|
||||
},
|
||||
};
|
||||
|
||||
static int fg_get_irq_index_byname(const char *name)
|
||||
|
|
@ -1638,6 +1740,11 @@ static int fg_parse_dt(struct fg_chip *chip)
|
|||
}
|
||||
}
|
||||
|
||||
rc = fg_get_batt_profile(chip);
|
||||
if (rc < 0)
|
||||
pr_warn("profile for batt_id=%dKOhms not found..using OTP, rc:%d\n",
|
||||
chip->batt_id, rc);
|
||||
|
||||
/* Read all the optional properties below */
|
||||
rc = of_property_read_u32(node, "qcom,fg-cutoff-voltage", &temp);
|
||||
if (rc < 0)
|
||||
|
|
@ -1724,6 +1831,9 @@ static int fg_parse_dt(struct fg_chip *chip)
|
|||
if (chip->cyc_ctr.en)
|
||||
chip->cyc_ctr.id = 1;
|
||||
|
||||
chip->dt.force_load_profile = of_property_read_bool(node,
|
||||
"qcom,fg-force-load-profile");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1836,10 +1946,8 @@ static int fg_gen3_probe(struct platform_device *pdev)
|
|||
goto exit;
|
||||
}
|
||||
|
||||
rc = fg_batt_profile_init(chip);
|
||||
if (rc < 0)
|
||||
dev_warn(chip->dev, "Error in initializing battery profile, rc:%d\n",
|
||||
rc);
|
||||
if (chip->profile_available)
|
||||
schedule_delayed_work(&chip->profile_load_work, 0);
|
||||
|
||||
device_init_wakeup(chip->dev, true);
|
||||
pr_debug("FG GEN3 driver successfully probed\n");
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue