From d6a8e003e07e1ebafc596e051defb84194c527a2 Mon Sep 17 00:00:00 2001 From: xiaonian Date: Thu, 16 Jul 2015 14:39:32 +0800 Subject: [PATCH] mmc: core: set REL_WR_SEC_C register to 0x1 per eMMC5.0 spec Some eMMC vendors violate eMMC 5.0 spec and set REL_WR_SEC_C register to 0x10 to indicate the ability of RPMB throughput improvement thus lead to failure when TZ module write data to RPMB partition. This change will check bit[4] of EXT_CSD[166] and if it is not set then change value of REL_WR_SEC_C to 0x1 directly ignoring value of EXT_CSD[222]. CRs-Fixed: 866059 Change-Id: Ibd12c94ad691eca1fa3ea2049b750a6e98178678 Signed-off-by: xiaonian Signed-off-by: Pavan Anamula --- drivers/mmc/core/mmc.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 818a70b4007d..052cd335490d 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -563,6 +563,19 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd) card->ext_csd.rel_param = ext_csd[EXT_CSD_WR_REL_PARAM]; card->ext_csd.rst_n_function = ext_csd[EXT_CSD_RST_N_FUNCTION]; + /* + * Some eMMC vendors violate eMMC 5.0 spec and set + * REL_WR_SEC_C register to 0x10 to indicate the + * ability of RPMB throughput improvement thus lead + * to failure when TZ module write data to RPMB + * partition. So check bit[4] of EXT_CSD[166] and + * if it is not set then change value of REL_WR_SEC_C + * to 0x1 directly ignoring value of EXT_CSD[222]. + */ + if (!(card->ext_csd.rel_param & + EXT_CSD_WR_REL_PARAM_EN_RPMB_REL_WR)) + card->ext_csd.rel_sectors = 0x1; + /* * RPMB regions are defined in multiples of 128K. */