msm: mdss: make timing db property DSI controller specific

If timing db(Double Buffered) property is enabled, then MDP FLUSH
bit needs to be set in order to push the data to video interface.
Currently this property is used as a shared property for both DSI
interfaces. But in case of chipsets where there is no FLUSH bit
defined for the secondary DSI interface, this will cause issue.
So moving the property to each controller specific instead of shared.

Change-Id: I25913867da41ca2fb2848ab96f5be5d9228a8f63
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>

Documentation/devicetree/bindings/fb/mdss-dsi.txt

@@ -65,7 +65,6 @@ Optional properties:
 					the default value for single DSI is set as PLL0.
 - qcom,mmss-ulp-clamp-ctrl-offset:	Specifies the offset for dsi ulps clamp control register.
 - qcom,mmss-phyreset-ctrl-offset:	Specifies the offset for dsi phy reset control register.
-- qcom,timing-db-mode:			Boolean specifies dsi timing mode registers are supported or not.
 - qcom,dsi-clk-ln-recovery:		Boolean which enables the clk lane recovery
 
 mdss-dsi-ctrl is a dsi controller device which is treated as a subnode of the mdss-dsi device.
@@ -123,6 +122,7 @@ Optional properties:
 					"lane_map_2103" = <2 1 0 3>
 					"lane_map_3210" = <3 2 1 0>
 - qcom,pluggable			Boolean to enable hotplug feature.
+- qcom,timing-db-mode:			Boolean specifies dsi timing mode registers are supported or not.
 
 Example:
 	mdss_dsi: qcom,mdss_dsi@0 {
@@ -138,7 +138,6 @@ Example:
 		      0x1a98780 0x1a98780 0x30
 		      0x193e000 0x193e000 0x30>;
 
-		qcom,timing-db-mode;
 		qcom,dsi-clk-ln-recovery;
 
 		qcom,core-supply-entries {
@@ -226,6 +225,7 @@ Example:
 			qcom,mmss-phyreset-ctrl-offset = <0x24>;
 			qcom,regulator-ldo-mode;
 			qcom,null-insertion-enabled;
+			qcom,timing-db-mode;
 
 			pinctrl-names = "mdss_default", "mdss_sleep";
 			pinctrl-0 = <&mdss_dsi_active>;

drivers/video/fbdev/msm/mdss_dsi.c

@@ -1663,7 +1663,7 @@ static void __mdss_dsi_update_video_mode_total(struct mdss_panel_data *pdata,
 				(new_dsi_v_total & 0x7ffffff));
 	}
 
-	if (ctrl_pdata->shared_data->timing_db_mode)
+	if (ctrl_pdata->timing_db_mode)
 		MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e4, 0x1);
 
 	pr_debug("%s new_fps:%d vsync:%d hsync:%d frame_rate:%d\n",
@@ -1672,7 +1672,7 @@ static void __mdss_dsi_update_video_mode_total(struct mdss_panel_data *pdata,
 
 	ctrl_pdata->panel_data.panel_info.current_fps = new_fps;
 	MDSS_XLOG(current_dsi_v_total, new_dsi_v_total, new_fps,
-		ctrl_pdata->shared_data->timing_db_mode);
+		ctrl_pdata->timing_db_mode);
 
 }
 
@@ -2986,9 +2986,6 @@ static int mdss_dsi_parse_dt_params(struct platform_device *pdev,
 				&sdata->ulps_phyrst_ctrl_off);
 	}
 
-	sdata->timing_db_mode = of_property_read_bool(
-		pdev->dev.of_node, "qcom,timing-db-mode");
-
 	sdata->cmd_clk_ln_recovery_en =
 		of_property_read_bool(pdev->dev.of_node,
 		"qcom,dsi-clk-ln-recovery");
@@ -3581,6 +3578,9 @@ static int mdss_dsi_parse_ctrl_params(struct platform_device *ctrl_pdev,
 			pinfo->mipi.dsi_phy_db.lanecfg[i] = data[i];
 	}
 
+	ctrl_pdata->timing_db_mode = of_property_read_bool(
+		ctrl_pdev->dev.of_node, "qcom,timing-db-mode");
+
 	ctrl_pdata->cmd_sync_wait_broadcast = of_property_read_bool(
 		pan_node, "qcom,cmd-sync-wait-broadcast");
 

drivers/video/fbdev/msm/mdss_dsi.h

@@ -240,7 +240,6 @@ struct dsi_shared_data {
 	u32 ulps_clamp_ctrl_off;
 	u32 ulps_phyrst_ctrl_off;
 
-	bool timing_db_mode;
 	bool cmd_clk_ln_recovery_en;
 	bool dsi0_active;
 	bool dsi1_active;
@@ -533,6 +532,7 @@ struct mdss_dsi_ctrl_pdata {
 
 	struct workqueue_struct *workq;
 	struct delayed_work dba_work;
+	bool timing_db_mode;
 };
 
 struct dsi_status_data {

drivers/video/fbdev/msm/mdss_dsi_host.c

@@ -1203,7 +1203,7 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata)
 		vsync_period = vspw + vbp + height + dummy_yres + vfp;
 		hsync_period = hspw + hbp + width + dummy_xres + hfp;
 
-		if (ctrl_pdata->shared_data->timing_db_mode)
+		if (ctrl_pdata->timing_db_mode)
 			MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e8, 0x1);
 		MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x24,
 			((hspw + hbp + width + dummy_xres) << 16 |
@@ -1218,7 +1218,7 @@ static void mdss_dsi_mode_setup(struct mdss_panel_data *pdata)
 		MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x30, (hspw << 16));
 		MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x34, 0);
 		MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x38, (vspw << 16));
-		if (ctrl_pdata->shared_data->timing_db_mode)
+		if (ctrl_pdata->timing_db_mode)
 			MIPI_OUTP((ctrl_pdata->ctrl_base) + 0x1e4, 0x1);
 	} else {		/* command mode */
 		if (mipi->dst_format == DSI_CMD_DST_FORMAT_RGB888)