staging: comedi: ni_stc.h: tidy up Interrupt_Control_Register and bits
Rename the CamelCase. Use the BIT() macro to define the bits. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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3 changed files with 19 additions and 18 deletions
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@ -354,7 +354,7 @@ static const struct mio_regmap m_series_stc_write_regmap[] = {
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[NISTC_CLK_FOUT_REG] = { 0x170, 2 },
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[NISTC_CLK_FOUT_REG] = { 0x170, 2 },
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[NISTC_IO_BIDIR_PIN_REG] = { 0x172, 2 },
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[NISTC_IO_BIDIR_PIN_REG] = { 0x172, 2 },
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[NISTC_RTSI_TRIG_DIR_REG] = { 0x174, 2 },
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[NISTC_RTSI_TRIG_DIR_REG] = { 0x174, 2 },
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[Interrupt_Control_Register] = { 0x176, 2 },
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[NISTC_INT_CTRL_REG] = { 0x176, 2 },
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[AI_Output_Control_Register] = { 0x178, 2 },
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[AI_Output_Control_Register] = { 0x178, 2 },
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[Analog_Trigger_Etc_Register] = { 0x17a, 2 },
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[Analog_Trigger_Etc_Register] = { 0x17a, 2 },
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[AI_START_STOP_Select_Register] = { 0x17c, 2 },
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[AI_START_STOP_Select_Register] = { 0x17c, 2 },
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@ -5389,12 +5389,13 @@ static int ni_E_init(struct comedi_device *dev,
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if (dev->irq) {
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if (dev->irq) {
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ni_stc_writew(dev,
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ni_stc_writew(dev,
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(irq_polarity ? Interrupt_Output_Polarity : 0) |
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(irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
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(Interrupt_Output_On_3_Pins & 0) |
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(NISTC_INT_CTRL_3PIN_INT & 0) |
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Interrupt_A_Enable | Interrupt_B_Enable |
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NISTC_INT_CTRL_INTA_ENA |
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Interrupt_A_Output_Select(interrupt_pin) |
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NISTC_INT_CTRL_INTB_ENA |
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Interrupt_B_Output_Select(interrupt_pin),
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NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
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Interrupt_Control_Register);
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NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
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NISTC_INT_CTRL_REG);
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}
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}
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/* DMA setup */
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/* DMA setup */
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@ -1085,7 +1085,7 @@ static void init_6143(struct comedi_device *dev)
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struct ni_private *devpriv = dev->private;
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struct ni_private *devpriv = dev->private;
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/* Disable interrupts */
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/* Disable interrupts */
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ni_stc_writew(dev, 0, Interrupt_Control_Register);
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ni_stc_writew(dev, 0, NISTC_INT_CTRL_REG);
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/* Initialise 6143 AI specific bits */
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/* Initialise 6143 AI specific bits */
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@ -285,6 +285,16 @@
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#define NISTC_RTSI_TRIG_USE_CLK BIT(1)
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#define NISTC_RTSI_TRIG_USE_CLK BIT(1)
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#define NISTC_RTSI_TRIG_DRV_CLK BIT(0)
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#define NISTC_RTSI_TRIG_DRV_CLK BIT(0)
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#define NISTC_INT_CTRL_REG 59
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#define NISTC_INT_CTRL_INTB_ENA BIT(15)
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#define NISTC_INT_CTRL_INTB_SEL(x) (((x) & 0x7) << 12)
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#define NISTC_INT_CTRL_INTA_ENA BIT(11)
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#define NISTC_INT_CTRL_INTA_SEL(x) (((x) & 0x7) << 8)
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#define NISTC_INT_CTRL_PASSTHRU0_POL BIT(3)
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#define NISTC_INT_CTRL_PASSTHRU1_POL BIT(2)
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#define NISTC_INT_CTRL_3PIN_INT BIT(1)
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#define NISTC_INT_CTRL_INT_POL BIT(0)
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#define AI_Status_1_Register 2
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#define AI_Status_1_Register 2
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#define Interrupt_A_St 0x8000
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#define Interrupt_A_St 0x8000
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#define AI_FIFO_Full_St 0x4000
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#define AI_FIFO_Full_St 0x4000
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@ -343,16 +353,6 @@ enum Joint_Status_2_Bits {
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#define AO_BC_Save_Registers 18
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#define AO_BC_Save_Registers 18
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#define AO_UC_Save_Registers 20
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#define AO_UC_Save_Registers 20
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#define Interrupt_Control_Register 59
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#define Interrupt_B_Enable _bit15
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#define Interrupt_B_Output_Select(x) ((x)<<12)
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#define Interrupt_A_Enable _bit11
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#define Interrupt_A_Output_Select(x) ((x)<<8)
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#define Pass_Thru_0_Interrupt_Polarity _bit3
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#define Pass_Thru_1_Interrupt_Polarity _bit2
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#define Interrupt_Output_On_3_Pins _bit1
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#define Interrupt_Output_Polarity _bit0
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#define AI_Output_Control_Register 60
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#define AI_Output_Control_Register 60
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#define AI_START_Output_Select _bit10
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#define AI_START_Output_Select _bit10
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#define AI_SCAN_IN_PROG_Output_Select(x) (((x) & 0x3) << 8)
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#define AI_SCAN_IN_PROG_Output_Select(x) (((x) & 0x3) << 8)
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