msm: kgsl: Force all command level context switches to the GPU

Force any command triggered context switch to the GPU - it should
be on the GPU anyway, but we were already passing a flags parameter
(unused) so this is a good chance to force the issue and make sure
that the cpu path decision isn't in play here.

CRs-Fixed: 1009124
Change-Id: Ic0dedbadb277a6498d0840b45c90e1265e2f354a
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>

drivers/gpu/msm/adreno_drawctxt.c

@@ -452,7 +452,7 @@ void adreno_drawctxt_detach(struct kgsl_context *context)
 	struct adreno_device *adreno_dev;
 	struct adreno_context *drawctxt;
 	struct adreno_ringbuffer *rb;
-	int ret, count, i;
+	int ret = 0, count, i;
 	struct kgsl_cmdbatch *list[ADRENO_CONTEXT_CMDQUEUE_SIZE];
 
 	if (context == NULL)
@@ -567,7 +567,7 @@ void adreno_drawctxt_destroy(struct kgsl_context *context)
  * @adreno_dev - The 3D device that owns the context
  * @rb: The ringubffer pointer on which the current context is being changed
  * @drawctxt - the 3D context to switch to
- * @flags - Flags to accompany the switch (from user space)
+ * @flags: Control flags for the switch
  *
  * Switch the current draw context in given RB
  */
@@ -597,8 +597,7 @@ int adreno_drawctxt_switch(struct adreno_device *adreno_dev,
 	if (drawctxt != NULL && kgsl_context_detached(&drawctxt->base))
 		return -ENOENT;
 
-	trace_adreno_drawctxt_switch(rb,
+	trace_adreno_drawctxt_switch(rb, drawctxt);
-		drawctxt, flags);
 
 	/* Get a refcount to the new instance */
 	if (drawctxt) {
@@ -610,7 +609,7 @@ int adreno_drawctxt_switch(struct adreno_device *adreno_dev,
 		 /* No context - set the default pagetable and thats it. */
 		new_pt = device->mmu.defaultpagetable;
 	}
-	ret = adreno_ringbuffer_set_pt_ctx(rb, new_pt, drawctxt);
+	ret = adreno_ringbuffer_set_pt_ctx(rb, new_pt, drawctxt, flags);
 	if (ret)
 		return ret;
 

drivers/gpu/msm/adreno_drawctxt.h

@@ -104,6 +104,9 @@ enum adreno_context_priv {
 	ADRENO_CONTEXT_SKIP_CMD,
 };
 
+/* Flags for adreno_drawctxt_switch() */
+#define ADRENO_CONTEXT_SWITCH_FORCE_GPU BIT(0)
+
 struct kgsl_context *adreno_drawctxt_create(struct kgsl_device_private *,
 			uint32_t *flags);
 

drivers/gpu/msm/adreno_iommu.c

@@ -847,7 +847,8 @@ int adreno_iommu_init(struct adreno_device *adreno_dev)
  */
 int adreno_iommu_set_pt_ctx(struct adreno_ringbuffer *rb,
 			struct kgsl_pagetable *new_pt,
-			struct adreno_context *drawctxt)
+			struct adreno_context *drawctxt,
+			unsigned long flags)
 {
 	struct adreno_device *adreno_dev = ADRENO_RB_DEVICE(rb);
 	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
@@ -858,7 +859,8 @@ int adreno_iommu_set_pt_ctx(struct adreno_ringbuffer *rb,
 	if (rb->drawctxt_active)
 		cur_pt = rb->drawctxt_active->base.proc_priv->pagetable;
 
-	cpu_path = _ctx_switch_use_cpu_path(adreno_dev, new_pt, rb);
+	cpu_path = !(flags & ADRENO_CONTEXT_SWITCH_FORCE_GPU) &&
+		_ctx_switch_use_cpu_path(adreno_dev, new_pt, rb);
 
 	/* Pagetable switch */
 	if (new_pt != cur_pt) {

drivers/gpu/msm/adreno_iommu.h

@@ -17,7 +17,8 @@
 #ifdef CONFIG_QCOM_KGSL_IOMMU
 int adreno_iommu_set_pt_ctx(struct adreno_ringbuffer *rb,
 			struct kgsl_pagetable *new_pt,
-			struct adreno_context *drawctxt);
+			struct adreno_context *drawctxt,
+			unsigned long flags);
 
 int adreno_iommu_init(struct adreno_device *adreno_dev);
 
@@ -33,7 +34,8 @@ static inline int adreno_iommu_init(struct adreno_device *adreno_dev)
 
 static inline int adreno_iommu_set_pt_ctx(struct adreno_ringbuffer *rb,
 			struct kgsl_pagetable *new_pt,
-			struct adreno_context *drawctxt)
+			struct adreno_context *drawctxt,
+			unsigned long flags)
 {
 	return 0;
 }

drivers/gpu/msm/adreno_ringbuffer.c

@@ -986,7 +986,9 @@ int adreno_ringbuffer_submitcmd(struct adreno_device *adreno_dev,
 	*cmds++ = cp_packet(adreno_dev, CP_NOP, 1);
 	*cmds++ = KGSL_END_OF_IB_IDENTIFIER;
 
-	ret = adreno_drawctxt_switch(adreno_dev, rb, drawctxt, cmdbatch->flags);
+	/* Context switches commands should *always* be on the GPU */
+	ret = adreno_drawctxt_switch(adreno_dev, rb, drawctxt,
+		ADRENO_CONTEXT_SWITCH_FORCE_GPU);
 
 	/*
 	 * In the unlikely event of an error in the drawctxt switch,

drivers/gpu/msm/adreno_ringbuffer.h

@@ -203,9 +203,10 @@ static inline unsigned int adreno_ringbuffer_dec_wrapped(unsigned int val,
 }
 
 static inline int adreno_ringbuffer_set_pt_ctx(struct adreno_ringbuffer *rb,
-		struct kgsl_pagetable *pt, struct adreno_context *context)
+		struct kgsl_pagetable *pt, struct adreno_context *context,
+		unsigned long flags)
 {
-	return adreno_iommu_set_pt_ctx(rb, pt, context);
+	return adreno_iommu_set_pt_ctx(rb, pt, context, flags);
 }
 
 #endif  /* __ADRENO_RINGBUFFER_H */

drivers/gpu/msm/adreno_trace.h

@@ -267,9 +267,8 @@ TRACE_EVENT(adreno_drawctxt_wait_done,
 
 TRACE_EVENT(adreno_drawctxt_switch,
 	TP_PROTO(struct adreno_ringbuffer *rb,
-		struct adreno_context *newctx,
+		struct adreno_context *newctx),
-		unsigned int flags),
+	TP_ARGS(rb, newctx),
-	TP_ARGS(rb, newctx, flags),
 	TP_STRUCT__entry(
 		__field(int, rb_level)
 		__field(unsigned int, oldctx)
@@ -283,8 +282,8 @@ TRACE_EVENT(adreno_drawctxt_switch,
 		__entry->newctx = newctx ? newctx->base.id : 0;
 	),
 	TP_printk(
-		"rb level=%d oldctx=%u newctx=%u flags=%X",
+		"rb level=%d oldctx=%u newctx=%u",
-		__entry->rb_level, __entry->oldctx, __entry->newctx, flags
+		__entry->rb_level, __entry->oldctx, __entry->newctx
 	)
 );