mmc: sdhci-msm: Fix clock gating while voltage switch is in progress

CLK_PWRSAVE bit in vendor specific register gates the output clock to
card automatically if there are no data/cmd operations.

According the SD3.0 voltage switch sequence the host should provide
clock to the card for atleast one millisecond before DAT[3:0] lines
are pulled high by the card. In this case if power save bit is enabled
it might auto-gate clocks even before the card completes voltage
switch sequence.

Fix this by disabling power save operation when the clocks are turned
off and enable only when clock rate is >400KHz i.e., end of initialization.

CRs-Fixed: 589992
Change-Id: If82d6d2e303b8d1189b76712e514f41fe6e2cf8b
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
This commit is contained in:
Sujit Reddy Thumma 2014-01-10 10:58:54 +05:30 committed by Subhash Jadavani
parent e8279c9021
commit d90d5901fa

View file

@ -2,7 +2,7 @@
* drivers/mmc/host/sdhci-msm.c - Qualcomm Technologies, Inc. MSM SDHCI Platform
* driver source file
*
* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@ -2453,6 +2453,12 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
bool curr_pwrsave;
if (!clock) {
/*
* disable pwrsave to ensure clock is not auto-gated until
* the rate is >400KHz (initialization complete).
*/
writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) &
~CORE_CLK_PWRSAVE, host->ioaddr + CORE_VENDOR_SPEC);
sdhci_msm_prepare_clocks(host, false);
host->clock = clock;
goto out;