mmc: sdhci-msm: Fix clock gating while voltage switch is in progress
CLK_PWRSAVE bit in vendor specific register gates the output clock to card automatically if there are no data/cmd operations. According the SD3.0 voltage switch sequence the host should provide clock to the card for atleast one millisecond before DAT[3:0] lines are pulled high by the card. In this case if power save bit is enabled it might auto-gate clocks even before the card completes voltage switch sequence. Fix this by disabling power save operation when the clocks are turned off and enable only when clock rate is >400KHz i.e., end of initialization. CRs-Fixed: 589992 Change-Id: If82d6d2e303b8d1189b76712e514f41fe6e2cf8b Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
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1 changed files with 7 additions and 1 deletions
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@ -2,7 +2,7 @@
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* drivers/mmc/host/sdhci-msm.c - Qualcomm Technologies, Inc. MSM SDHCI Platform
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* driver source file
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*
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* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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* Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -2453,6 +2453,12 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
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bool curr_pwrsave;
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if (!clock) {
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/*
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* disable pwrsave to ensure clock is not auto-gated until
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* the rate is >400KHz (initialization complete).
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*/
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writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) &
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~CORE_CLK_PWRSAVE, host->ioaddr + CORE_VENDOR_SPEC);
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sdhci_msm_prepare_clocks(host, false);
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host->clock = clock;
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goto out;
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