msm: pcie: update debugfs messages with new IPC label
In addition to having outputs to kernel log, PCIe debugfs messages should also be captured in IPC logging. Therefore, add a new IPC logging label and update the existing calls to do so. Change-Id: I2ab6a6549575c4e2de2f1ef0756328f4b6f6a178 Signed-off-by: Tony Truong <truong@codeaurora.org>
This commit is contained in:
Tony Truong
David Keitel
parent
d4eaaf3a8a
commit
d9d95976d1
1 changed files with 128 additions and 103 deletions
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@ -324,6 +324,13 @@
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"DUMP:%s: " fmt, __func__, arg); \
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} while (0)
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#define PCIE_DBG_FS(dev, fmt, arg...) do { \
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if ((dev) && (dev)->ipc_log_dump) \
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ipc_log_string((dev)->ipc_log_dump, \
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"DBG_FS:%s: " fmt, __func__, arg); \
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pr_alert("%s: " fmt, __func__, arg); \
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} while (0)
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#define PCIE_INFO(dev, fmt, arg...) do { \
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if ((dev) && (dev)->ipc_log_long) \
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ipc_log_string((dev)->ipc_log_long, \
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@ -1422,92 +1429,92 @@ static void pcie_parf_dump(struct msm_pcie_dev_t *dev)
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static void msm_pcie_show_status(struct msm_pcie_dev_t *dev)
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{
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pr_alert("PCIe: RC%d is %s enumerated\n",
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PCIE_DBG_FS(dev, "PCIe: RC%d is %s enumerated\n",
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dev->rc_idx, dev->enumerated ? "" : "not");
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pr_alert("PCIe: link is %s\n",
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PCIE_DBG_FS(dev, "PCIe: link is %s\n",
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(dev->link_status == MSM_PCIE_LINK_ENABLED)
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? "enabled" : "disabled");
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pr_alert("cfg_access is %s allowed\n",
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PCIE_DBG_FS(dev, "cfg_access is %s allowed\n",
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dev->cfg_access ? "" : "not");
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pr_alert("use_msi is %d\n",
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PCIE_DBG_FS(dev, "use_msi is %d\n",
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dev->use_msi);
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pr_alert("use_pinctrl is %d\n",
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PCIE_DBG_FS(dev, "use_pinctrl is %d\n",
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dev->use_pinctrl);
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pr_alert("user_suspend is %d\n",
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PCIE_DBG_FS(dev, "user_suspend is %d\n",
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dev->user_suspend);
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pr_alert("num_ep: %d\n",
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PCIE_DBG_FS(dev, "num_ep: %d\n",
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dev->num_ep);
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pr_alert("num_active_ep: %d\n",
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PCIE_DBG_FS(dev, "num_active_ep: %d\n",
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dev->num_active_ep);
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pr_alert("pending_ep_reg: %s\n",
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PCIE_DBG_FS(dev, "pending_ep_reg: %s\n",
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dev->pending_ep_reg ? "true" : "false");
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pr_alert("disable_pc is %d",
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PCIE_DBG_FS(dev, "disable_pc is %d",
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dev->disable_pc);
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pr_alert("l0s_supported is %s supported\n",
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PCIE_DBG_FS(dev, "l0s_supported is %s supported\n",
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dev->l0s_supported ? "" : "not");
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pr_alert("l1_supported is %s supported\n",
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PCIE_DBG_FS(dev, "l1_supported is %s supported\n",
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dev->l1_supported ? "" : "not");
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pr_alert("l1ss_supported is %s supported\n",
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PCIE_DBG_FS(dev, "l1ss_supported is %s supported\n",
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dev->l1ss_supported ? "" : "not");
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pr_alert("common_clk_en is %d\n",
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PCIE_DBG_FS(dev, "common_clk_en is %d\n",
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dev->common_clk_en);
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pr_alert("clk_power_manage_en is %d\n",
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PCIE_DBG_FS(dev, "clk_power_manage_en is %d\n",
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dev->clk_power_manage_en);
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pr_alert("aux_clk_sync is %d\n",
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PCIE_DBG_FS(dev, "aux_clk_sync is %d\n",
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dev->aux_clk_sync);
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pr_alert("ext_ref_clk is %d\n",
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PCIE_DBG_FS(dev, "ext_ref_clk is %d\n",
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dev->ext_ref_clk);
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pr_alert("ep_wakeirq is %d\n",
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PCIE_DBG_FS(dev, "ep_wakeirq is %d\n",
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dev->ep_wakeirq);
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pr_alert("phy_ver is %d\n",
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PCIE_DBG_FS(dev, "phy_ver is %d\n",
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dev->phy_ver);
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pr_alert("drv_ready is %d\n",
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PCIE_DBG_FS(dev, "drv_ready is %d\n",
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dev->drv_ready);
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pr_alert("the link is %s suspending\n",
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PCIE_DBG_FS(dev, "the link is %s suspending\n",
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dev->suspending ? "" : "not");
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pr_alert("shadow is %s enabled\n",
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PCIE_DBG_FS(dev, "shadow is %s enabled\n",
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dev->shadow_en ? "" : "not");
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pr_alert("the power of RC is %s on\n",
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PCIE_DBG_FS(dev, "the power of RC is %s on\n",
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dev->power_on ? "" : "not");
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pr_alert("msi_gicm_addr: 0x%x\n",
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PCIE_DBG_FS(dev, "msi_gicm_addr: 0x%x\n",
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dev->msi_gicm_addr);
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pr_alert("msi_gicm_base: 0x%x\n",
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PCIE_DBG_FS(dev, "msi_gicm_base: 0x%x\n",
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dev->msi_gicm_base);
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pr_alert("bus_client: %d\n",
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PCIE_DBG_FS(dev, "bus_client: %d\n",
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dev->bus_client);
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pr_alert("current short bdf: %d\n",
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PCIE_DBG_FS(dev, "current short bdf: %d\n",
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dev->current_short_bdf);
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pr_alert("smmu does %s exist\n",
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PCIE_DBG_FS(dev, "smmu does %s exist\n",
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dev->smmu_exist ? "" : "not");
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pr_alert("n_fts: %d\n",
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PCIE_DBG_FS(dev, "n_fts: %d\n",
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dev->n_fts);
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pr_alert("common_phy: %d\n",
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PCIE_DBG_FS(dev, "common_phy: %d\n",
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dev->common_phy);
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pr_alert("ep_latency: %dms\n",
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PCIE_DBG_FS(dev, "ep_latency: %dms\n",
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dev->ep_latency);
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pr_alert("current_bdf: 0x%x\n",
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PCIE_DBG_FS(dev, "current_bdf: 0x%x\n",
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dev->current_bdf);
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pr_alert("tlp_rd_size: 0x%x\n",
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PCIE_DBG_FS(dev, "tlp_rd_size: 0x%x\n",
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dev->tlp_rd_size);
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pr_alert("rc_corr_counter: %lu\n",
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PCIE_DBG_FS(dev, "rc_corr_counter: %lu\n",
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dev->rc_corr_counter);
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pr_alert("rc_non_fatal_counter: %lu\n",
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PCIE_DBG_FS(dev, "rc_non_fatal_counter: %lu\n",
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dev->rc_non_fatal_counter);
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pr_alert("rc_fatal_counter: %lu\n",
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PCIE_DBG_FS(dev, "rc_fatal_counter: %lu\n",
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dev->rc_fatal_counter);
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pr_alert("ep_corr_counter: %lu\n",
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PCIE_DBG_FS(dev, "ep_corr_counter: %lu\n",
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dev->ep_corr_counter);
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pr_alert("ep_non_fatal_counter: %lu\n",
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PCIE_DBG_FS(dev, "ep_non_fatal_counter: %lu\n",
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dev->ep_non_fatal_counter);
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pr_alert("ep_fatal_counter: %lu\n",
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PCIE_DBG_FS(dev, "ep_fatal_counter: %lu\n",
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dev->ep_fatal_counter);
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pr_alert("linkdown_counter: %lu\n",
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PCIE_DBG_FS(dev, "linkdown_counter: %lu\n",
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dev->linkdown_counter);
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pr_alert("wake_counter: %lu\n",
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PCIE_DBG_FS(dev, "wake_counter: %lu\n",
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dev->wake_counter);
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pr_alert("link_turned_on_counter: %lu\n",
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PCIE_DBG_FS(dev, "link_turned_on_counter: %lu\n",
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dev->link_turned_on_counter);
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pr_alert("link_turned_off_counter: %lu\n",
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PCIE_DBG_FS(dev, "link_turned_off_counter: %lu\n",
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dev->link_turned_off_counter);
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}
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@ -1524,7 +1531,7 @@ static void msm_pcie_shadow_dump(struct msm_pcie_dev_t *dev, bool rc)
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shadow = dev->rc_shadow;
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} else {
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shadow = dev->ep_shadow[i];
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pr_alert("PCIe Device: %02x:%02x.%01x\n",
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PCIE_DBG_FS(dev, "PCIe Device: %02x:%02x.%01x\n",
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dev->pcidev_table[i].bdf >> 24,
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dev->pcidev_table[i].bdf >> 19 & 0x1f,
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dev->pcidev_table[i].bdf >> 16 & 0x07);
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@ -1532,7 +1539,8 @@ static void msm_pcie_shadow_dump(struct msm_pcie_dev_t *dev, bool rc)
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for (j = 0; j < PCIE_CONF_SPACE_DW; j++) {
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val = shadow[j];
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if (val != PCIE_CLEAR) {
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pr_alert("PCIe: shadow_dw[%d]:cfg 0x%x:0x%x\n",
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PCIE_DBG_FS(dev,
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"PCIe: shadow_dw[%d]:cfg 0x%x:0x%x\n",
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j, j * 4, val);
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}
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}
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@ -1581,33 +1589,35 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
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switch (testcase) {
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case 0: /* output status */
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pr_alert("\n\nPCIe: Status for RC%d:\n",
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PCIE_DBG_FS(dev, "\n\nPCIe: Status for RC%d:\n",
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dev->rc_idx);
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msm_pcie_show_status(dev);
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break;
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case 1: /* disable link */
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pr_alert("\n\nPCIe: RC%d: disable link\n\n", dev->rc_idx);
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PCIE_DBG_FS(dev,
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"\n\nPCIe: RC%d: disable link\n\n", dev->rc_idx);
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ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, 0,
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dev->dev, NULL,
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MSM_PCIE_CONFIG_NO_CFG_RESTORE);
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if (ret)
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pr_alert("PCIe:%s:failed to disable link\n",
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PCIE_DBG_FS(dev, "PCIe:%s:failed to disable link\n",
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__func__);
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else
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pr_alert("PCIe:%s:disabled link\n",
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PCIE_DBG_FS(dev, "PCIe:%s:disabled link\n",
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__func__);
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break;
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case 2: /* enable link and recover config space for RC and EP */
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pr_alert("\n\nPCIe: RC%d: enable link and recover config space\n\n",
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PCIE_DBG_FS(dev,
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"\n\nPCIe: RC%d: enable link and recover config space\n\n",
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dev->rc_idx);
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ret = msm_pcie_pm_control(MSM_PCIE_RESUME, 0,
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dev->dev, NULL,
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MSM_PCIE_CONFIG_NO_CFG_RESTORE);
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if (ret)
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pr_alert("PCIe:%s:failed to enable link\n",
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PCIE_DBG_FS(dev, "PCIe:%s:failed to enable link\n",
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__func__);
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else {
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pr_alert("PCIe:%s:enabled link\n", __func__);
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PCIE_DBG_FS(dev, "PCIe:%s:enabled link\n", __func__);
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msm_pcie_recover_config(dev->dev);
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}
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break;
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@ -1615,38 +1625,41 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
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* disable and enable link, recover config space for
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* RC and EP
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*/
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pr_alert("\n\nPCIe: RC%d: disable and enable link then recover config space\n\n",
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PCIE_DBG_FS(dev,
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"\n\nPCIe: RC%d: disable and enable link then recover config space\n\n",
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dev->rc_idx);
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ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, 0,
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dev->dev, NULL,
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MSM_PCIE_CONFIG_NO_CFG_RESTORE);
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if (ret)
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pr_alert("PCIe:%s:failed to disable link\n",
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PCIE_DBG_FS(dev, "PCIe:%s:failed to disable link\n",
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__func__);
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else
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pr_alert("PCIe:%s:disabled link\n", __func__);
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PCIE_DBG_FS(dev, "PCIe:%s:disabled link\n", __func__);
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ret = msm_pcie_pm_control(MSM_PCIE_RESUME, 0,
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dev->dev, NULL,
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MSM_PCIE_CONFIG_NO_CFG_RESTORE);
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if (ret)
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pr_alert("PCIe:%s:failed to enable link\n",
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PCIE_DBG_FS(dev, "PCIe:%s:failed to enable link\n",
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__func__);
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else {
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pr_alert("PCIe:%s:enabled link\n", __func__);
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PCIE_DBG_FS(dev, "PCIe:%s:enabled link\n", __func__);
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msm_pcie_recover_config(dev->dev);
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}
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break;
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case 4: /* dump shadow registers for RC and EP */
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pr_alert("\n\nPCIe: RC%d: dumping RC shadow registers\n",
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PCIE_DBG_FS(dev,
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"\n\nPCIe: RC%d: dumping RC shadow registers\n",
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dev->rc_idx);
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msm_pcie_shadow_dump(dev, true);
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pr_alert("\n\nPCIe: RC%d: dumping EP shadow registers\n",
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PCIE_DBG_FS(dev,
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"\n\nPCIe: RC%d: dumping EP shadow registers\n",
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dev->rc_idx);
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msm_pcie_shadow_dump(dev, false);
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break;
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case 5: /* disable L0s */
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pr_alert("\n\nPCIe: RC%d: disable L0s\n\n",
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PCIE_DBG_FS(dev, "\n\nPCIe: RC%d: disable L0s\n\n",
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dev->rc_idx);
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msm_pcie_write_mask(dev->dm_core +
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PCIE20_CAP_LINKCTRLSTATUS,
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@ -1662,15 +1675,15 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
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readl_relaxed(dev->conf +
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ep_link_ctrlstts_offset);
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}
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pr_alert("PCIe: RC's CAP_LINKCTRLSTATUS:0x%x\n",
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PCIE_DBG_FS(dev, "PCIe: RC's CAP_LINKCTRLSTATUS:0x%x\n",
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readl_relaxed(dev->dm_core +
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PCIE20_CAP_LINKCTRLSTATUS));
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pr_alert("PCIe: EP's CAP_LINKCTRLSTATUS:0x%x\n",
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PCIE_DBG_FS(dev, "PCIe: EP's CAP_LINKCTRLSTATUS:0x%x\n",
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readl_relaxed(dev->conf +
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ep_link_ctrlstts_offset));
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break;
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case 6: /* enable L0s */
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pr_alert("\n\nPCIe: RC%d: enable L0s\n\n",
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PCIE_DBG_FS(dev, "\n\nPCIe: RC%d: enable L0s\n\n",
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dev->rc_idx);
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msm_pcie_write_mask(dev->dm_core +
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PCIE20_CAP_LINKCTRLSTATUS,
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@ -1686,15 +1699,15 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
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readl_relaxed(dev->conf +
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ep_link_ctrlstts_offset);
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}
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pr_alert("PCIe: RC's CAP_LINKCTRLSTATUS:0x%x\n",
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PCIE_DBG_FS(dev, "PCIe: RC's CAP_LINKCTRLSTATUS:0x%x\n",
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readl_relaxed(dev->dm_core +
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PCIE20_CAP_LINKCTRLSTATUS));
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pr_alert("PCIe: EP's CAP_LINKCTRLSTATUS:0x%x\n",
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PCIE_DBG_FS(dev, "PCIe: EP's CAP_LINKCTRLSTATUS:0x%x\n",
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readl_relaxed(dev->conf +
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ep_link_ctrlstts_offset));
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break;
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case 7: /* disable L1 */
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pr_alert("\n\nPCIe: RC%d: disable L1\n\n",
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PCIE_DBG_FS(dev, "\n\nPCIe: RC%d: disable L1\n\n",
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dev->rc_idx);
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msm_pcie_write_mask(dev->dm_core +
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PCIE20_CAP_LINKCTRLSTATUS,
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@ -1710,15 +1723,15 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
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readl_relaxed(dev->conf +
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ep_link_ctrlstts_offset);
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}
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pr_alert("PCIe: RC's CAP_LINKCTRLSTATUS:0x%x\n",
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PCIE_DBG_FS(dev, "PCIe: RC's CAP_LINKCTRLSTATUS:0x%x\n",
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readl_relaxed(dev->dm_core +
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PCIE20_CAP_LINKCTRLSTATUS));
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pr_alert("PCIe: EP's CAP_LINKCTRLSTATUS:0x%x\n",
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PCIE_DBG_FS(dev, "PCIe: EP's CAP_LINKCTRLSTATUS:0x%x\n",
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readl_relaxed(dev->conf +
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ep_link_ctrlstts_offset));
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break;
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case 8: /* enable L1 */
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pr_alert("\n\nPCIe: RC%d: enable L1\n\n",
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PCIE_DBG_FS(dev, "\n\nPCIe: RC%d: enable L1\n\n",
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dev->rc_idx);
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msm_pcie_write_mask(dev->dm_core +
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PCIE20_CAP_LINKCTRLSTATUS,
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@ -1734,15 +1747,15 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
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readl_relaxed(dev->conf +
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ep_link_ctrlstts_offset);
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}
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pr_alert("PCIe: RC's CAP_LINKCTRLSTATUS:0x%x\n",
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PCIE_DBG_FS(dev, "PCIe: RC's CAP_LINKCTRLSTATUS:0x%x\n",
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readl_relaxed(dev->dm_core +
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PCIE20_CAP_LINKCTRLSTATUS));
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pr_alert("PCIe: EP's CAP_LINKCTRLSTATUS:0x%x\n",
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PCIE_DBG_FS(dev, "PCIe: EP's CAP_LINKCTRLSTATUS:0x%x\n",
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readl_relaxed(dev->conf +
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ep_link_ctrlstts_offset));
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break;
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case 9: /* disable L1ss */
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pr_alert("\n\nPCIe: RC%d: disable L1ss\n\n",
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PCIE_DBG_FS(dev, "\n\nPCIe: RC%d: disable L1ss\n\n",
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dev->rc_idx);
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current_offset = PCIE_EXT_CAP_OFFSET;
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while (current_offset) {
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@ -1755,12 +1768,13 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
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current_offset = val >> 20;
|
||||
}
|
||||
if (!ep_l1sub_ctrl1_offset) {
|
||||
pr_alert("PCIe: RC%d endpoint does not support l1ss registers\n",
|
||||
PCIE_DBG_FS(dev,
|
||||
"PCIe: RC%d endpoint does not support l1ss registers\n",
|
||||
dev->rc_idx);
|
||||
break;
|
||||
}
|
||||
|
||||
pr_alert("PCIe: RC%d: ep_l1sub_ctrl1_offset: 0x%x\n",
|
||||
PCIE_DBG_FS(dev, "PCIe: RC%d: ep_l1sub_ctrl1_offset: 0x%x\n",
|
||||
dev->rc_idx, ep_l1sub_ctrl1_offset);
|
||||
|
||||
msm_pcie_write_reg_field(dev->dm_core,
|
||||
|
|
@ -1789,21 +1803,21 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
|
|||
readl_relaxed(dev->conf +
|
||||
ep_dev_ctrl2stts2_offset);
|
||||
}
|
||||
pr_alert("PCIe: RC's L1SUB_CONTROL1:0x%x\n",
|
||||
PCIE_DBG_FS(dev, "PCIe: RC's L1SUB_CONTROL1:0x%x\n",
|
||||
readl_relaxed(dev->dm_core +
|
||||
PCIE20_L1SUB_CONTROL1));
|
||||
pr_alert("PCIe: RC's DEVICE_CONTROL2_STATUS2:0x%x\n",
|
||||
PCIE_DBG_FS(dev, "PCIe: RC's DEVICE_CONTROL2_STATUS2:0x%x\n",
|
||||
readl_relaxed(dev->dm_core +
|
||||
PCIE20_DEVICE_CONTROL2_STATUS2));
|
||||
pr_alert("PCIe: EP's L1SUB_CONTROL1:0x%x\n",
|
||||
PCIE_DBG_FS(dev, "PCIe: EP's L1SUB_CONTROL1:0x%x\n",
|
||||
readl_relaxed(dev->conf +
|
||||
ep_l1sub_ctrl1_offset));
|
||||
pr_alert("PCIe: EP's DEVICE_CONTROL2_STATUS2:0x%x\n",
|
||||
PCIE_DBG_FS(dev, "PCIe: EP's DEVICE_CONTROL2_STATUS2:0x%x\n",
|
||||
readl_relaxed(dev->conf +
|
||||
ep_dev_ctrl2stts2_offset));
|
||||
break;
|
||||
case 10: /* enable L1ss */
|
||||
pr_alert("\n\nPCIe: RC%d: enable L1ss\n\n",
|
||||
PCIE_DBG_FS(dev, "\n\nPCIe: RC%d: enable L1ss\n\n",
|
||||
dev->rc_idx);
|
||||
current_offset = PCIE_EXT_CAP_OFFSET;
|
||||
while (current_offset) {
|
||||
|
|
@ -1818,7 +1832,8 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
|
|||
current_offset = val >> 20;
|
||||
}
|
||||
if (!ep_l1sub_ctrl1_offset) {
|
||||
pr_alert("PCIe: RC%d endpoint does not support l1ss registers\n",
|
||||
PCIE_DBG_FS(dev,
|
||||
"PCIe: RC%d endpoint does not support l1ss registers\n",
|
||||
dev->rc_idx);
|
||||
break;
|
||||
}
|
||||
|
|
@ -1826,9 +1841,9 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
|
|||
val = readl_relaxed(dev->conf +
|
||||
ep_l1sub_cap_reg1_offset);
|
||||
|
||||
pr_alert("PCIe: EP's L1SUB_CAPABILITY_REG_1: 0x%x\n",
|
||||
PCIE_DBG_FS(dev, "PCIe: EP's L1SUB_CAPABILITY_REG_1: 0x%x\n",
|
||||
val);
|
||||
pr_alert("PCIe: RC%d: ep_l1sub_ctrl1_offset: 0x%x\n",
|
||||
PCIE_DBG_FS(dev, "PCIe: RC%d: ep_l1sub_ctrl1_offset: 0x%x\n",
|
||||
dev->rc_idx, ep_l1sub_ctrl1_offset);
|
||||
|
||||
val &= 0xf;
|
||||
|
|
@ -1859,44 +1874,48 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
|
|||
readl_relaxed(dev->conf +
|
||||
ep_dev_ctrl2stts2_offset);
|
||||
}
|
||||
pr_alert("PCIe: RC's L1SUB_CONTROL1:0x%x\n",
|
||||
PCIE_DBG_FS(dev, "PCIe: RC's L1SUB_CONTROL1:0x%x\n",
|
||||
readl_relaxed(dev->dm_core +
|
||||
PCIE20_L1SUB_CONTROL1));
|
||||
pr_alert("PCIe: RC's DEVICE_CONTROL2_STATUS2:0x%x\n",
|
||||
PCIE_DBG_FS(dev, "PCIe: RC's DEVICE_CONTROL2_STATUS2:0x%x\n",
|
||||
readl_relaxed(dev->dm_core +
|
||||
PCIE20_DEVICE_CONTROL2_STATUS2));
|
||||
pr_alert("PCIe: EP's L1SUB_CONTROL1:0x%x\n",
|
||||
PCIE_DBG_FS(dev, "PCIe: EP's L1SUB_CONTROL1:0x%x\n",
|
||||
readl_relaxed(dev->conf +
|
||||
ep_l1sub_ctrl1_offset));
|
||||
pr_alert("PCIe: EP's DEVICE_CONTROL2_STATUS2:0x%x\n",
|
||||
PCIE_DBG_FS(dev, "PCIe: EP's DEVICE_CONTROL2_STATUS2:0x%x\n",
|
||||
readl_relaxed(dev->conf +
|
||||
ep_dev_ctrl2stts2_offset));
|
||||
break;
|
||||
case 11: /* enumerate PCIe */
|
||||
pr_alert("\n\nPCIe: attempting to enumerate RC%d\n\n",
|
||||
PCIE_DBG_FS(dev, "\n\nPCIe: attempting to enumerate RC%d\n\n",
|
||||
dev->rc_idx);
|
||||
if (dev->enumerated)
|
||||
pr_alert("PCIe: RC%d is already enumerated\n",
|
||||
PCIE_DBG_FS(dev, "PCIe: RC%d is already enumerated\n",
|
||||
dev->rc_idx);
|
||||
else {
|
||||
if (!msm_pcie_enumerate(dev->rc_idx))
|
||||
pr_alert("PCIe: RC%d is successfully enumerated\n",
|
||||
PCIE_DBG_FS(dev,
|
||||
"PCIe: RC%d is successfully enumerated\n",
|
||||
dev->rc_idx);
|
||||
else
|
||||
pr_alert("PCIe: RC%d enumeration failed\n",
|
||||
PCIE_DBG_FS(dev,
|
||||
"PCIe: RC%d enumeration failed\n",
|
||||
dev->rc_idx);
|
||||
}
|
||||
break;
|
||||
case 12: /* write a value to a register */
|
||||
pr_alert("\n\nPCIe: RC%d: writing a value to a register\n\n",
|
||||
PCIE_DBG_FS(dev,
|
||||
"\n\nPCIe: RC%d: writing a value to a register\n\n",
|
||||
dev->rc_idx);
|
||||
|
||||
if (!base_sel) {
|
||||
pr_alert("Invalid base_sel: 0x%x\n", base_sel);
|
||||
PCIE_DBG_FS(dev, "Invalid base_sel: 0x%x\n", base_sel);
|
||||
break;
|
||||
}
|
||||
|
||||
pr_alert("base: %s: 0x%p\nwr_offset: 0x%x\nwr_mask: 0x%x\nwr_value: 0x%x\n",
|
||||
PCIE_DBG_FS(dev,
|
||||
"base: %s: 0x%p\nwr_offset: 0x%x\nwr_mask: 0x%x\nwr_value: 0x%x\n",
|
||||
dev->res[base_sel - 1].name,
|
||||
dev->res[base_sel - 1].base,
|
||||
wr_offset, wr_mask, wr_value);
|
||||
|
|
@ -1907,7 +1926,7 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
|
|||
break;
|
||||
case 13: /* dump all registers of base_sel */
|
||||
if (!base_sel) {
|
||||
pr_alert("Invalid base_sel: 0x%x\n", base_sel);
|
||||
PCIE_DBG_FS(dev, "Invalid base_sel: 0x%x\n", base_sel);
|
||||
break;
|
||||
} else if (base_sel - 1 == MSM_PCIE_RES_PHY) {
|
||||
pcie_phy_dump(dev);
|
||||
|
|
@ -1919,11 +1938,12 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
|
|||
dev->res[base_sel - 1].resource);
|
||||
}
|
||||
|
||||
pr_alert("\n\nPCIe: Dumping %s Registers for RC%d\n\n",
|
||||
PCIE_DBG_FS(dev, "\n\nPCIe: Dumping %s Registers for RC%d\n\n",
|
||||
dev->res[base_sel - 1].name, dev->rc_idx);
|
||||
|
||||
for (i = 0; i < base_sel_size; i += 32) {
|
||||
pr_alert("0x%04x %08x %08x %08x %08x %08x %08x %08x %08x\n",
|
||||
PCIE_DBG_FS(dev,
|
||||
"0x%04x %08x %08x %08x %08x %08x %08x %08x %08x\n",
|
||||
i, readl_relaxed(dev->res[base_sel - 1].base + i),
|
||||
readl_relaxed(dev->res[base_sel - 1].base + (i + 4)),
|
||||
readl_relaxed(dev->res[base_sel - 1].base + (i + 8)),
|
||||
|
|
@ -1935,7 +1955,7 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
|
|||
}
|
||||
break;
|
||||
default:
|
||||
pr_alert("Invalid testcase: %d.\n", testcase);
|
||||
PCIE_DBG_FS(dev, "Invalid testcase: %d.\n", testcase);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -1953,12 +1973,14 @@ int msm_pcie_debug_info(struct pci_dev *dev, u32 option, u32 base,
|
|||
|
||||
if (option == 12 || option == 13) {
|
||||
if (!base || base > 5) {
|
||||
pr_alert("Invalid base_sel: 0x%x\n", base);
|
||||
pr_alert("PCIe: base_sel is still 0x%x\n", base_sel);
|
||||
PCIE_DBG_FS(pdev, "Invalid base_sel: 0x%x\n", base);
|
||||
PCIE_DBG_FS(pdev,
|
||||
"PCIe: base_sel is still 0x%x\n", base_sel);
|
||||
return -EINVAL;
|
||||
} else {
|
||||
base_sel = base;
|
||||
pr_alert("PCIe: base_sel is now 0x%x\n", base_sel);
|
||||
PCIE_DBG_FS(pdev,
|
||||
"PCIe: base_sel is now 0x%x\n", base_sel);
|
||||
}
|
||||
|
||||
if (option == 12) {
|
||||
|
|
@ -1966,9 +1988,12 @@ int msm_pcie_debug_info(struct pci_dev *dev, u32 option, u32 base,
|
|||
wr_mask = mask;
|
||||
wr_value = value;
|
||||
|
||||
pr_alert("PCIe: wr_offset is now 0x%x\n", wr_offset);
|
||||
pr_alert("PCIe: wr_mask is now 0x%x\n", wr_mask);
|
||||
pr_alert("PCIe: wr_value is now 0x%x\n", wr_value);
|
||||
PCIE_DBG_FS(pdev,
|
||||
"PCIe: wr_offset is now 0x%x\n", wr_offset);
|
||||
PCIE_DBG_FS(pdev,
|
||||
"PCIe: wr_mask is now 0x%x\n", wr_mask);
|
||||
PCIE_DBG_FS(pdev,
|
||||
"PCIe: wr_value is now 0x%x\n", wr_value);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue