ARM: ux500: Enable Cortex-A9 GIC (Generic Interrupt Controller) in Device Tree
This enables the embedded GIC on all u8500 based hardware using DT. Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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2 changed files with 24 additions and 1 deletions
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@ -16,8 +16,19 @@
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <1>;
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compatible = "stericsson,db8500";
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compatible = "stericsson,db8500";
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interrupt-parent = <&intc>;
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ranges;
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ranges;
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intc: interrupt-controller@a0411000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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interrupt-parent;
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reg = <0xa0411000 0x1000>,
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<0xa0410100 0x100>;
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};
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pmu {
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pmu {
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compatible = "arm,cortex-a9-pmu";
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 7 0x4>;
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interrupts = <0 7 0x4>;
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@ -16,6 +16,8 @@
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#include <linux/err.h>
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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#include <linux/stat.h>
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#include <linux/stat.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <asm/hardware/gic.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach/map.h>
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#include <asm/mach/map.h>
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@ -28,6 +30,11 @@
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void __iomem *_PRCMU_BASE;
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void __iomem *_PRCMU_BASE;
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static const struct of_device_id ux500_dt_irq_match[] = {
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{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
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{},
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};
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void __init ux500_init_irq(void)
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void __init ux500_init_irq(void)
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{
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{
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void __iomem *dist_base;
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void __iomem *dist_base;
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@ -42,7 +49,12 @@ void __init ux500_init_irq(void)
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} else
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} else
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ux500_unknown_soc();
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ux500_unknown_soc();
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gic_init(0, 29, dist_base, cpu_base);
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#ifdef CONFIG_OF
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if (of_have_populated_dt())
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of_irq_init(ux500_dt_irq_match);
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else
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#endif
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gic_init(0, 29, dist_base, cpu_base);
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/*
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/*
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* Init clocks here so that they are available for system timer
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* Init clocks here so that they are available for system timer
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