clk: msm: mdss: Export DSI1 PLL clocks

Add support for all the clocks provided by the DSI1 PLL in preparation
for supporting two independent displays using the two DSI controllers.

Change-Id: I9c9e4cddd23be869d9f16a5c3e1351a88f88699f
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
[cip@codeaurora.org: Removed .dtsi file updates]
Signed-off-by: Clarence Ip <cip@codeaurora.org>

drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c

@@ -68,8 +68,8 @@ int post_n1_div_set_div(struct div_clk *clk, int div)
 	pout->pll_postdiv = 1;	/* fixed, divided by 1 */
 	pout->pll_n1div  = div;
 
-	pr_debug("div=%d postdiv=%x n1div=%x\n",
-			div, pout->pll_postdiv, pout->pll_n1div);
+	pr_debug("ndx=%d div=%d postdiv=%x n1div=%x\n",
+			pll->index, div, pout->pll_postdiv, pout->pll_n1div);
 
 	/* registers commited at pll_db_commit_8996() */
 
@@ -139,7 +139,7 @@ int n2_div_set_div(struct div_clk *clk, int div)
 
 	/* set dsiclk_sel=1 so that n2div *= 2 */
 	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CLK_CFG1, 1);
-	pr_debug("div=%d n2div=%x\n", div, n2div);
+	pr_debug("ndx=%d div=%d n2div=%x\n", pll->index, div, n2div);
 
 	mdss_pll_resource_enable(pll, false);
 
@@ -157,7 +157,8 @@ int n2_div_get_div(struct div_clk *clk)
 
 	rc = mdss_pll_resource_enable(pll, true);
 	if (rc) {
-		pr_err("Failed to enable mdss dsi pll resources\n");
+		pr_err("Failed to enable mdss dsi pll=%d resources\n",
+						pll->index);
 		return rc;
 	}
 
@@ -167,7 +168,7 @@ int n2_div_get_div(struct div_clk *clk)
 
 	mdss_pll_resource_enable(pll, false);
 
-	pr_debug("div=%d\n", n2div);
+	pr_debug("ndx=%d div=%d\n", pll->index, n2div);
 
 	return n2div;
 }
@@ -184,7 +185,8 @@ static bool pll_is_pll_locked_8996(struct mdss_pll_resources *pll)
 			((status & BIT(5)) > 0),
 			DSI_PLL_POLL_MAX_READS,
 			DSI_PLL_POLL_TIMEOUT_US)) {
-		pr_debug("DSI PLL status=%x failed to Lock\n", status);
+			pr_err("DSI PLL ndx=%d status=%x failed to Lock\n",
+					pll->index, status);
 		pll_locked = false;
 	} else if (readl_poll_timeout_atomic((pll->pll_base +
 				DSIPHY_PLL_RESET_SM_READY_STATUS),
@@ -192,7 +194,8 @@ static bool pll_is_pll_locked_8996(struct mdss_pll_resources *pll)
 				((status & BIT(0)) > 0),
 				DSI_PLL_POLL_MAX_READS,
 				DSI_PLL_POLL_TIMEOUT_US)) {
-		pr_debug("DSI PLL status=%x PLl not ready\n", status);
+			pr_err("DSI PLL ndx=%d status=%x PLl not ready\n",
+					pll->index, status);
 		pll_locked = false;
 	} else {
 		pll_locked = true;
@@ -232,12 +235,12 @@ int dsi_pll_enable_seq_8996(struct mdss_pll_resources *pll)
 	 */
 
 	if (!pll_is_pll_locked_8996(pll)) {
-		pr_err("DSI PLL lock failed\n");
+		pr_err("DSI PLL ndx=%d lock failed\n", pll->index);
 		rc = -EINVAL;
 		goto init_lock_err;
 	}
 
-	pr_debug("DSI PLL Lock success\n");
+	pr_debug("DSI PLL ndx=%d Lock success\n", pll->index);
 
 init_lock_err:
 	return rc;
@@ -251,7 +254,8 @@ static int dsi_pll_enable(struct clk *c)
 
 	rc = mdss_pll_resource_enable(pll, true);
 	if (rc) {
-		pr_err("Failed to enable mdss dsi pll resources\n");
+		pr_err("ndx=%d Failed to enable mdss dsi pll resources\n",
+							pll->index);
 		return rc;
 	}
 
@@ -266,7 +270,7 @@ static int dsi_pll_enable(struct clk *c)
 
 	if (rc) {
 		mdss_pll_resource_enable(pll, false);
-		pr_err("DSI PLL failed to lock\n");
+		pr_err("ndx=%d DSI PLL failed to lock\n", pll->index);
 	} else {
 		pll->pll_on = true;
 	}
@@ -282,7 +286,7 @@ static void dsi_pll_disable(struct clk *c)
 
 	if (!pll->pll_on &&
 		mdss_pll_resource_enable(pll, true)) {
-		pr_err("Failed to enable mdss dsi pll resources\n");
+		pr_err("Failed to enable mdss dsi pll=%d\n", pll->index);
 		return;
 	}
 
@@ -311,7 +315,7 @@ static void dsi_pll_disable(struct clk *c)
 
 	pll->pll_on = false;
 
-	pr_debug("DSI PLL Disabled\n");
+	pr_debug("DSI PLL ndx=%d Disabled\n", pll->index);
 	return;
 }
 
@@ -621,11 +625,12 @@ int pll_vco_set_rate_8996(struct clk *c, unsigned long rate)
 
 	rc = mdss_pll_resource_enable(pll, true);
 	if (rc) {
-		pr_err("Failed to enable mdss dsi pll resources\n");
+		pr_err("Failed to enable mdss dsi plla=%d\n", pll->index);
 		return rc;
 	}
 
-	pr_debug("%s: rate=%lu\n", __func__, rate);
+	pr_debug("%s: ndx=%d base=%p rate=%lu\n", __func__,
+				pll->index, pll->pll_base, rate);
 
 	pll->vco_current_rate = rate;
 	pll->vco_ref_clk_rate = vco->ref_clk_rate;
@@ -665,7 +670,7 @@ unsigned long pll_vco_get_rate_8996(struct clk *c)
 
 	rc = mdss_pll_resource_enable(pll, true);
 	if (rc) {
-		pr_err("Failed to enable mdss dsi pll resources\n");
+		pr_err("Failed to enable mdss dsi pll=%d\n", pll->index);
 		return rc;
 	}
 
@@ -725,7 +730,7 @@ enum handoff pll_vco_handoff_8996(struct clk *c)
 
 	rc = mdss_pll_resource_enable(pll, true);
 	if (rc) {
-		pr_err("Failed to enable mdss dsi pll resources\n");
+		pr_err("Failed to enable mdss dsi pll=%d\n", pll->index);
 		return ret;
 	}
 
@@ -756,7 +761,8 @@ int pll_vco_prepare_8996(struct clk *c)
 	    && (pll->vco_cached_rate == c->rate)) {
 		rc = c->ops->set_rate(c, pll->vco_cached_rate);
 		if (rc) {
-			pr_err("vco_set_rate failed. rc=%d\n", rc);
+			pr_err("index=%d vco_set_rate failed. rc=%d\n",
+					rc, pll->index);
 			goto error;
 		}
 	}

drivers/clk/msm/mdss/mdss-dsi-pll-8996.c

@@ -28,7 +28,7 @@
 
 #define VCO_DELAY_USEC		1
 
-static struct dsi_pll_db pll_db;
+static struct dsi_pll_db pll_db[DSI_PLL_NUM];
 
 static struct clk_ops n2_clk_src_ops;
 static struct clk_ops byte_clk_src_ops;
@@ -65,114 +65,223 @@ static struct clk_mux_ops mdss_pixel_mux_ops = {
 	.get_mux_sel = get_mdss_pixel_mux_sel_8996,
 };
 
-static struct dsi_pll_vco_clk dsi_vco_clk = {
+static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
 	.ref_clk_rate = 19200000,
 	.min_rate = 1300000000,
 	.max_rate = 2600000000,
 	.pll_en_seq_cnt = 1,
 	.pll_enable_seqs[0] = dsi_pll_enable_seq_8996,
 	.c = {
-		.dbg_name = "dsi_vco_clk_8996",
+		.dbg_name = "dsi0pll_vco_clk_8996",
 		.ops = &clk_ops_dsi_vco,
-		CLK_INIT(dsi_vco_clk.c),
+		CLK_INIT(dsi0pll_vco_clk.c),
 	},
 };
 
-static struct div_clk post_n1_div_clk = {
+static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
+	.ref_clk_rate = 19200000,
+	.min_rate = 1300000000,
+	.max_rate = 2600000000,
+	.pll_en_seq_cnt = 1,
+	.pll_enable_seqs[0] = dsi_pll_enable_seq_8996,
+	.c = {
+		.dbg_name = "dsi1pll_vco_clk_8996",
+		.ops = &clk_ops_dsi_vco,
+		CLK_INIT(dsi1pll_vco_clk.c),
+	},
+};
+
+static struct div_clk dsi0pll_post_n1_div_clk = {
 	.data = {
 		.max_div = 15,
 		.min_div = 1,
 	},
 	.ops = &post_n1_div_ops,
 	.c = {
-		.parent = &dsi_vco_clk.c,
-		.dbg_name = "post_n1_div_clk",
+		.parent = &dsi0pll_vco_clk.c,
+		.dbg_name = "dsi0pll_post_n1_div_clk",
 		.ops = &post_n1_div_clk_src_ops,
 		.flags = CLKFLAG_NO_RATE_CACHE,
-		CLK_INIT(post_n1_div_clk.c),
+		CLK_INIT(dsi0pll_post_n1_div_clk.c),
 	},
 };
 
-static struct div_clk n2_div_clk = {
+static struct div_clk dsi1pll_post_n1_div_clk = {
+	.data = {
+		.max_div = 15,
+		.min_div = 1,
+	},
+	.ops = &post_n1_div_ops,
+	.c = {
+		.parent = &dsi1pll_vco_clk.c,
+		.dbg_name = "dsi1pll_post_n1_div_clk",
+		.ops = &post_n1_div_clk_src_ops,
+		.flags = CLKFLAG_NO_RATE_CACHE,
+		CLK_INIT(dsi1pll_post_n1_div_clk.c),
+	},
+};
+
+static struct div_clk dsi0pll_n2_div_clk = {
 	.data = {
 		.max_div = 15,
 		.min_div = 1,
 	},
 	.ops = &n2_div_ops,
 	.c = {
-		.parent = &post_n1_div_clk.c,
-		.dbg_name = "n2_div_clk",
+		.parent = &dsi0pll_post_n1_div_clk.c,
+		.dbg_name = "dsi0pll_n2_div_clk",
 		.ops = &n2_clk_src_ops,
 		.flags = CLKFLAG_NO_RATE_CACHE,
-		CLK_INIT(n2_div_clk.c),
+		CLK_INIT(dsi0pll_n2_div_clk.c),
 	},
 };
 
-static struct div_clk pixel_clk_src = {
+static struct div_clk dsi1pll_n2_div_clk = {
+	.data = {
+		.max_div = 15,
+		.min_div = 1,
+	},
+	.ops = &n2_div_ops,
+	.c = {
+		.parent = &dsi1pll_post_n1_div_clk.c,
+		.dbg_name = "dsi1pll_n2_div_clk",
+		.ops = &n2_clk_src_ops,
+		.flags = CLKFLAG_NO_RATE_CACHE,
+		CLK_INIT(dsi1pll_n2_div_clk.c),
+	},
+};
+
+static struct div_clk dsi0pll_pixel_clk_src = {
 	.data = {
 		.div = 2,
 		.min_div = 2,
 		.max_div = 2,
 	},
 	.c = {
-		.parent = &n2_div_clk.c,
-		.dbg_name = "pixel_clk_src",
+		.parent = &dsi0pll_n2_div_clk.c,
+		.dbg_name = "dsi0pll_pixel_clk_src_0",
 		.ops = &clk_ops_div,
 		.flags = CLKFLAG_NO_RATE_CACHE,
-		CLK_INIT(pixel_clk_src.c),
+		CLK_INIT(dsi0pll_pixel_clk_src.c),
 	},
 };
 
-static struct mux_clk mdss_pixel_clk_mux = {
+static struct div_clk dsi1pll_pixel_clk_src = {
+	.data = {
+		.div = 2,
+		.min_div = 2,
+		.max_div = 2,
+	},
+	.c = {
+		.parent = &dsi1pll_n2_div_clk.c,
+		.dbg_name = "dsi1pll_pixel_clk_src",
+		.ops = &clk_ops_div,
+		.flags = CLKFLAG_NO_RATE_CACHE,
+		CLK_INIT(dsi1pll_pixel_clk_src.c),
+	},
+};
+
+static struct mux_clk dsi0pll_pixel_clk_mux = {
 	.num_parents = 1,
 	.parents = (struct clk_src[]) {
-		{&pixel_clk_src.c, 0},
+		{&dsi0pll_pixel_clk_src.c, 0},
 	},
 	.ops = &mdss_pixel_mux_ops,
 	.c = {
-		.parent = &pixel_clk_src.c,
-		.dbg_name = "mdss_pixel_clk_mux",
+		.parent = &dsi0pll_pixel_clk_src.c,
+		.dbg_name = "dsi0pll_pixel_clk_mux_0",
 		.ops = &clk_ops_gen_mux,
-		CLK_INIT(mdss_pixel_clk_mux.c),
+		CLK_INIT(dsi0pll_pixel_clk_mux.c),
 	}
 };
 
-static struct div_clk byte_clk_src = {
+static struct mux_clk dsi1pll_pixel_clk_mux = {
+	.num_parents = 1,
+	.parents = (struct clk_src[]) {
+		{&dsi1pll_pixel_clk_src.c, 0},
+	},
+	.ops = &mdss_pixel_mux_ops,
+	.c = {
+		.parent = &dsi1pll_pixel_clk_src.c,
+		.dbg_name = "dsi1pll_pixel_clk_mux",
+		.ops = &clk_ops_gen_mux,
+		CLK_INIT(dsi1pll_pixel_clk_mux.c),
+	}
+};
+
+static struct div_clk dsi0pll_byte_clk_src = {
 	.data = {
 		.div = 8,
 		.min_div = 8,
 		.max_div = 8,
 	},
 	.c = {
-		.parent = &post_n1_div_clk.c,
-		.dbg_name = "byte_clk_src",
+		.parent = &dsi0pll_post_n1_div_clk.c,
+		.dbg_name = "dsi0pll_byte_clk_src",
 		.ops = &clk_ops_div,
-		CLK_INIT(byte_clk_src.c),
+		CLK_INIT(dsi0pll_byte_clk_src.c),
 	},
 };
 
-static struct mux_clk mdss_byte_clk_mux = {
+static struct div_clk dsi1pll_byte_clk_src = {
+	.data = {
+		.div = 8,
+		.min_div = 8,
+		.max_div = 8,
+	},
+	.c = {
+		.parent = &dsi1pll_post_n1_div_clk.c,
+		.dbg_name = "dsi1pll_byte_clk_src",
+		.ops = &clk_ops_div,
+		CLK_INIT(dsi1pll_byte_clk_src.c),
+	},
+};
+
+static struct mux_clk dsi0pll_byte_clk_mux = {
 	.num_parents = 1,
 	.parents = (struct clk_src[]) {
-		{&byte_clk_src.c, 0},
+		{&dsi0pll_byte_clk_src.c, 0},
 	},
 	.ops = &mdss_byte_mux_ops,
 	.c = {
-		.parent = &byte_clk_src.c,
-		.dbg_name = "mdss_byte_clk_mux",
+		.parent = &dsi0pll_byte_clk_src.c,
+		.dbg_name = "dsi0pll_byte_clk_mux",
 		.ops = &clk_ops_gen_mux_dsi,
-		CLK_INIT(mdss_byte_clk_mux.c),
+		CLK_INIT(dsi0pll_byte_clk_mux.c),
+	}
+};
+static struct mux_clk dsi1pll_byte_clk_mux = {
+	.num_parents = 1,
+	.parents = (struct clk_src[]) {
+		{&dsi1pll_byte_clk_src.c, 0},
+	},
+	.ops = &mdss_byte_mux_ops,
+	.c = {
+		.parent = &dsi1pll_byte_clk_src.c,
+		.dbg_name = "dsi1pll_byte_clk_mux",
+		.ops = &clk_ops_gen_mux_dsi,
+		CLK_INIT(dsi1pll_byte_clk_mux.c),
 	}
 };
 
 static struct clk_lookup mdss_dsi_pllcc_8996[] = {
-	CLK_LIST(mdss_byte_clk_mux),
-	CLK_LIST(byte_clk_src),
-	CLK_LIST(mdss_pixel_clk_mux),
-	CLK_LIST(pixel_clk_src),
-	CLK_LIST(n2_div_clk),
-	CLK_LIST(post_n1_div_clk),
-	CLK_LIST(dsi_vco_clk),
+	CLK_LIST(dsi0pll_byte_clk_mux),
+	CLK_LIST(dsi0pll_byte_clk_src),
+	CLK_LIST(dsi0pll_pixel_clk_mux),
+	CLK_LIST(dsi0pll_pixel_clk_src),
+	CLK_LIST(dsi0pll_n2_div_clk),
+	CLK_LIST(dsi0pll_post_n1_div_clk),
+	CLK_LIST(dsi0pll_vco_clk),
+};
+
+static struct clk_lookup mdss_dsi_pllcc_8996_1[] = {
+	CLK_LIST(dsi1pll_byte_clk_mux),
+	CLK_LIST(dsi1pll_byte_clk_src),
+	CLK_LIST(dsi1pll_pixel_clk_mux),
+	CLK_LIST(dsi1pll_pixel_clk_src),
+	CLK_LIST(dsi1pll_n2_div_clk),
+	CLK_LIST(dsi1pll_post_n1_div_clk),
+	CLK_LIST(dsi1pll_vco_clk),
 };
 
 int dsi_pll_clock_register_8996(struct platform_device *pdev,
@@ -191,11 +300,16 @@ int dsi_pll_clock_register_8996(struct platform_device *pdev,
 		return -EPROBE_DEFER;
 	}
 
-	pr_debug("ndx=%d is_slave=%d\n", pll_res->index, pll_res->is_slave);
+	pr_err("ndx=%d is_slave=%d\n", pll_res->index, pll_res->is_slave);
+
+	if (pll_res->index >= DSI_PLL_NUM) {
+		pr_err("pll ndx=%d is NOT supported\n", pll_res->index);
+		return -EINVAL;
+	}
 
 	if (!pll_res->is_slave) {
 		/* master at split display or stand alone */
-		pll_res->priv = &pll_db;
+		pll_res->priv = &pll_db[pll_res->index];
 		master_pll = pll_res;	/* keep master pll */
 	} else {
 		/* slave pll */
@@ -207,18 +321,6 @@ int dsi_pll_clock_register_8996(struct platform_device *pdev,
 		master_pll->slave = pll_res;
 		return 0;	/* done for slave */
 	}
-	/*
-	 * Set client data to mux, div and vco clocks.
-	 * This needs to be done only for PLL0 since, that is the one in
-	 * use.
-	 **/
-	byte_clk_src.priv = pll_res;
-	pixel_clk_src.priv = pll_res;
-	post_n1_div_clk.priv = pll_res;
-	n2_div_clk.priv = pll_res;
-	dsi_vco_clk.priv = pll_res;
-
-	pll_res->vco_delay = VCO_DELAY_USEC;
 
 	/* Set clock source operations */
 
@@ -237,18 +339,35 @@ int dsi_pll_clock_register_8996(struct platform_device *pdev,
 	clk_ops_gen_mux_dsi.round_rate = parent_round_rate;
 	clk_ops_gen_mux_dsi.set_rate = parent_set_rate;
 
-	if (pll_res->target_id == MDSS_PLL_TARGET_8996) {
+	/* Set client data to mux, div and vco clocks.  */
+	if (pll_res->index == DSI_PLL_1) {
+		dsi1pll_byte_clk_src.priv = pll_res;
+		dsi1pll_pixel_clk_src.priv = pll_res;
+		dsi1pll_post_n1_div_clk.priv = pll_res;
+		dsi1pll_n2_div_clk.priv = pll_res;
+		dsi1pll_vco_clk.priv = pll_res;
+
+		pll_res->vco_delay = VCO_DELAY_USEC;
+		rc = of_msm_clock_register(pdev->dev.of_node,
+				mdss_dsi_pllcc_8996_1,
+				ARRAY_SIZE(mdss_dsi_pllcc_8996_1));
+	} else {
+		dsi0pll_byte_clk_src.priv = pll_res;
+		dsi0pll_pixel_clk_src.priv = pll_res;
+		dsi0pll_post_n1_div_clk.priv = pll_res;
+		dsi0pll_n2_div_clk.priv = pll_res;
+		dsi0pll_vco_clk.priv = pll_res;
+
+		pll_res->vco_delay = VCO_DELAY_USEC;
 		rc = of_msm_clock_register(pdev->dev.of_node,
 				mdss_dsi_pllcc_8996,
 				ARRAY_SIZE(mdss_dsi_pllcc_8996));
-		if (rc) {
-			pr_err("Clock register failed\n");
-			rc = -EPROBE_DEFER;
-		}
 	}
 
-	if (!rc)
-		pr_info("Registered DSI PLL clocks successfully\n");
+	if (!rc) {
+		pr_info("Registered DSI PLL ndx=%d clocks successfully\n",
+						pll_res->index);
+	}
 
 	return rc;
 }

drivers/clk/msm/mdss/mdss-dsi-pll-8996.h

@@ -139,6 +139,12 @@ struct dsi_pll_output {
 	u32 fcvo;
 };
 
+enum {
+	DSI_PLL_0,
+	DSI_PLL_1,
+	DSI_PLL_NUM
+};
+
 struct dsi_pll_db {
 	struct dsi_pll_input in;
 	struct dsi_pll_output out;

drivers/clk/msm/mdss/mdss-pll.c

@@ -176,8 +176,10 @@ static int mdss_pll_clock_register(struct platform_device *pdev,
 		break;
 	}
 
-	if (rc)
-		pr_err("Pll parent clock register failed rc=%d\n", rc);
+	if (rc) {
+		pr_err("Pll ndx=%d clock register failed rc=%d\n",
+				pll_res->index, rc);
+	}
 
 	return rc;
 }
@@ -239,6 +241,9 @@ static int mdss_pll_probe(struct platform_device *pdev)
 		goto io_error;
 	}
 
+	pr_debug("%s: ndx=%d base=%p\n", __func__,
+			pll_res->index, pll_res->pll_base);
+
 	rc = mdss_pll_resource_parse(pdev, pll_res);
 	if (rc) {
 		pr_err("Pll resource parsing from dt failed rc=%d\n", rc);
@@ -286,13 +291,15 @@ static int mdss_pll_probe(struct platform_device *pdev)
 
 	rc = mdss_pll_resource_init(pdev, pll_res);
 	if (rc) {
-		pr_err("Pll resource init failed rc=%d\n", rc);
+		pr_err("Pll ndx=%d resource init failed rc=%d\n",
+				pll_res->index, rc);
 		goto res_init_error;
 	}
 
 	rc = mdss_pll_clock_register(pdev, pll_res);
 	if (rc) {
-		pr_err("Pll clock register failed rc=%d\n", rc);
+		pr_err("Pll ndx=%d clock register failed rc=%d\n",
+			pll_res->index, rc);
 		goto clock_register_error;
 	}
 

drivers/video/fbdev/msm/msm_mdss_io_8974.c

@@ -719,7 +719,7 @@ int mdss_dsi_pll_1_clk_init(struct platform_device *pdev,
 	}
 
 	dev = &pdev->dev;
-	ctrl->vco_clk = clk_get(dev, "clk_mdss_dsi1_vco_clk_src");
+	ctrl->vco_clk = clk_get(dev, "pll1_vco_clk_src");
 	if (IS_ERR(ctrl->vco_clk)) {
 		rc = PTR_ERR(ctrl->vco_clk);
 		pr_err("%s: can't find vco_clk. rc=%d\n",
@@ -759,7 +759,7 @@ int mdss_dsi_shadow_clk_init(struct platform_device *pdev,
 	}
 
 	dev = &pdev->dev;
-	ctrl->mux_byte_clk = devm_clk_get(dev, "mdss_byte_clk_mux");
+	ctrl->mux_byte_clk = devm_clk_get(dev, "pll_byte_clk_mux");
 	if (IS_ERR(ctrl->mux_byte_clk)) {
 		rc = PTR_ERR(ctrl->mux_byte_clk);
 		pr_err("%s: can't find mux_byte_clk. rc=%d\n",
@@ -768,7 +768,7 @@ int mdss_dsi_shadow_clk_init(struct platform_device *pdev,
 		goto error;
 	}
 
-	ctrl->mux_pixel_clk = devm_clk_get(dev, "mdss_pixel_clk_mux");
+	ctrl->mux_pixel_clk = devm_clk_get(dev, "pll_pixel_clk_mux");
 	if (IS_ERR(ctrl->mux_pixel_clk)) {
 		rc = PTR_ERR(ctrl->mux_pixel_clk);
 		pr_err("%s: can't find mdss_mux_pixel_clk. rc=%d\n",
@@ -777,7 +777,7 @@ int mdss_dsi_shadow_clk_init(struct platform_device *pdev,
 		goto error;
 	}
 
-	ctrl->pll_byte_clk = devm_clk_get(dev, "byte_clk_src");
+	ctrl->pll_byte_clk = devm_clk_get(dev, "pll_byte_clk_src");
 	if (IS_ERR(ctrl->pll_byte_clk)) {
 		rc = PTR_ERR(ctrl->pll_byte_clk);
 		pr_err("%s: can't find pll_byte_clk. rc=%d\n",
@@ -786,7 +786,7 @@ int mdss_dsi_shadow_clk_init(struct platform_device *pdev,
 		goto error;
 	}
 
-	ctrl->pll_pixel_clk = devm_clk_get(dev, "pixel_clk_src");
+	ctrl->pll_pixel_clk = devm_clk_get(dev, "pll_pixel_clk_src");
 	if (IS_ERR(ctrl->pll_pixel_clk)) {
 		rc = PTR_ERR(ctrl->pll_pixel_clk);
 		pr_err("%s: can't find pll_pixel_clk. rc=%d\n",
@@ -795,7 +795,7 @@ int mdss_dsi_shadow_clk_init(struct platform_device *pdev,
 		goto error;
 	}
 
-	ctrl->shadow_byte_clk = devm_clk_get(dev, "shadow_byte_clk_src");
+	ctrl->shadow_byte_clk = devm_clk_get(dev, "pll_shadow_byte_clk_src");
 	if (IS_ERR(ctrl->shadow_byte_clk)) {
 		rc = PTR_ERR(ctrl->shadow_byte_clk);
 		pr_err("%s: can't find shadow_byte_clk. rc=%d\n",
@@ -804,7 +804,7 @@ int mdss_dsi_shadow_clk_init(struct platform_device *pdev,
 		goto error;
 	}
 
-	ctrl->shadow_pixel_clk = devm_clk_get(dev, "shadow_pixel_clk_src");
+	ctrl->shadow_pixel_clk = devm_clk_get(dev, "pll_shadow_pixel_clk_src");
 	if (IS_ERR(ctrl->shadow_pixel_clk)) {
 		rc = PTR_ERR(ctrl->shadow_pixel_clk);
 		pr_err("%s: can't find shadow_pixel_clk. rc=%d\n",