clk: msm: clock-mmss-cobalt: Add support for some display clocks
The mmss_mdss_byte0/1_intf_clk clocks are needed by the display driver. Add support to program them in the clock driver. CRs-Fixed: 981902 Change-Id: I17b1ecaec9c98261faa49c6f088c4802a716ecf7 Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
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2 changed files with 30 additions and 0 deletions
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@ -1747,6 +1747,18 @@ static struct branch_clk mmss_mdss_byte0_clk = {
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},
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};
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static struct branch_clk mmss_mdss_byte0_intf_clk = {
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.cbcr_reg = MMSS_MDSS_BYTE0_INTF_CBCR,
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.has_sibling = 1,
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.base = &virt_base,
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.c = {
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.dbg_name = "mmss_mdss_byte0_intf_clk",
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.parent = &byte0_clk_src.c,
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.ops = &clk_ops_branch,
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CLK_INIT(mmss_mdss_byte0_intf_clk.c),
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},
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};
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static struct branch_clk mmss_mdss_byte1_clk = {
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.cbcr_reg = MMSS_MDSS_BYTE1_CBCR,
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.has_sibling = 0,
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@ -1759,6 +1771,18 @@ static struct branch_clk mmss_mdss_byte1_clk = {
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},
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};
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static struct branch_clk mmss_mdss_byte1_intf_clk = {
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.cbcr_reg = MMSS_MDSS_BYTE1_INTF_CBCR,
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.has_sibling = 1,
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.base = &virt_base,
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.c = {
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.dbg_name = "mmss_mdss_byte1_intf_clk",
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.parent = &byte1_clk_src.c,
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.ops = &clk_ops_branch,
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CLK_INIT(mmss_mdss_byte1_intf_clk.c),
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},
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};
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static struct branch_clk mmss_mdss_dp_aux_clk = {
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.cbcr_reg = MMSS_MDSS_DP_AUX_CBCR,
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.has_sibling = 0,
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@ -2245,6 +2269,8 @@ static struct mux_clk mmss_debug_mux = {
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{ &mmss_throttle_camss_axi_clk.c, 0x00aa },
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{ &mmss_throttle_mdss_axi_clk.c, 0x00ab },
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{ &mmss_throttle_video_axi_clk.c, 0x00ac },
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{ &mmss_mdss_byte0_intf_clk.c, 0x00ad },
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{ &mmss_mdss_byte1_intf_clk.c, 0x00ae },
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),
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.c = {
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.dbg_name = "mmss_debug_mux",
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@ -2381,7 +2407,9 @@ static struct clk_lookup msm_clocks_mmss_cobalt[] = {
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CLK_LIST(mmss_mdss_ahb_clk),
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CLK_LIST(mmss_mdss_axi_clk),
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CLK_LIST(mmss_mdss_byte0_clk),
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CLK_LIST(mmss_mdss_byte0_intf_clk),
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CLK_LIST(mmss_mdss_byte1_clk),
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CLK_LIST(mmss_mdss_byte1_intf_clk),
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CLK_LIST(mmss_mdss_dp_aux_clk),
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CLK_LIST(mmss_mdss_dp_gtc_clk),
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CLK_LIST(mmss_mdss_esc0_clk),
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@ -397,7 +397,9 @@
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#define clk_mmss_mdss_ahb_clk 0x85d37ab5
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#define clk_mmss_mdss_axi_clk 0xdf04fc1d
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#define clk_mmss_mdss_byte0_clk 0x38105d25
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#define clk_mmss_mdss_byte0_intf_clk 0x38e5aa79
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#define clk_mmss_mdss_byte1_clk 0xe0c21354
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#define clk_mmss_mdss_byte1_intf_clk 0xcf654d8e
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#define clk_mmss_mdss_dp_aux_clk 0x23125eb6
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#define clk_mmss_mdss_dp_gtc_clk 0xb59c151a
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#define clk_mmss_mdss_esc0_clk 0x5721ff83
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