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ALSA: Fix for reading RIRB buffer on NVIDIA aza controller with AMD Phenom cpu

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When read RIRB buffer immediately after RIRB interrupt received,
sometimes the data will be "0x0". If we wait for some time, the data
in buffer will be correct. This issue only occurred with AMD Phenom cpu.
So we set this "needs_damn_long_delay" flag.

Signed-off-by: Wei Ni <wni@nvidia.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Jaroslav Kysela <perex@perex.cz>
This commit is contained in:
Wei Ni 2008-09-26 13:55:56 +08:00 • committed by Jaroslav Kysela
parent 9a10eb21e1
commit dc9c8e218d
1 changed files with 3 additions and 0 deletions
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3
sound/pci/hda/hda_intel.c
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@ -1220,6 +1220,9 @@ static int __devinit azx_codec_create(struct azx *chip, const char *model,
if (err < 0)
return err;
if (chip->driver_type == AZX_DRIVER_NVIDIA)
chip->bus->needs_damn_long_delay = 1;
codecs = audio_codecs = 0;
max_slots = azx_max_codecs[chip->driver_type];
if (!max_slots)