msm: mdss: hdmi: add new formats defined in cea-861-f
CEA-861-F specification defines new video formats which are supported in the hdmi 2.0 specification. Change-Id: I5bf017835ea7c5e472e91c0d663f6f0083a87854 Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
This commit is contained in:
Vinu Deokaran
David Keitel
parent
f98cc6f5dc
commit
dd24186a13
7 changed files with 326 additions and 92 deletions
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@ -123,6 +123,7 @@ struct hdmi_edid_ctrl {
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u8 spkr_alloc_data_block[MAX_SPKR_ALLOC_DATA_BLOCK_SIZE];
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int sadb_size;
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u8 edid_buf[MAX_EDID_BLOCK_SIZE];
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u32 max_pclk_khz;
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struct hdmi_edid_sink_data sink_data;
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struct hdmi_edid_init_data init_data;
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@ -311,6 +312,10 @@ static ssize_t hdmi_edid_sysfs_rda_res_info(struct device *dev,
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edid_ctrl->init_data.ds_data,
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minfo->video_format);
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info.pixel_formats =
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(minfo->rgb_support ? MSM_HDMI_RGB_888_24BPP_FORMAT : 0) |
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(minfo->y420_support ? MSM_HDMI_YUV_420_12BPP_FORMAT : 0);
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minfo++;
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if (ret || !info.supported)
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continue;
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@ -326,7 +331,7 @@ static ssize_t hdmi_edid_sysfs_rda_res_info(struct device *dev,
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memcpy(&info_dbg, buf_dbg, sizeof(info_dbg));
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DEV_DBG("%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\n",
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DEV_DBG("%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\n",
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info_dbg.video_format, info_dbg.active_h,
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info_dbg.front_porch_h, info_dbg.pulse_width_h,
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info_dbg.back_porch_h, info_dbg.active_low_h,
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@ -334,7 +339,8 @@ static ssize_t hdmi_edid_sysfs_rda_res_info(struct device *dev,
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info_dbg.pulse_width_v, info_dbg.back_porch_v,
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info_dbg.active_low_v, info_dbg.pixel_freq,
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info_dbg.refresh_rate, info_dbg.interlaced,
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info_dbg.supported, info_dbg.ar);
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info_dbg.supported, info_dbg.ar,
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info_dbg.pixel_formats);
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buf_dbg += sizeof(info_dbg);
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}
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@ -507,6 +513,15 @@ static struct attribute_group hdmi_edid_fs_attrs_group = {
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.attrs = hdmi_edid_fs_attrs,
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};
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static bool hdmi_edid_is_mode_supported(struct hdmi_edid_ctrl *edid_ctrl,
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struct msm_hdmi_mode_timing_info *timing)
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{
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if (!timing->supported || timing->pixel_freq > edid_ctrl->max_pclk_khz)
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return false;
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return true;
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}
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static int hdmi_edid_read_block(struct hdmi_edid_ctrl *edid_ctrl, int block,
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u8 *edid_buf)
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{
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@ -661,7 +676,7 @@ static void hdmi_edid_add_sink_y420_format(struct hdmi_edid_ctrl *edid_ctrl,
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u32 ret = hdmi_get_supported_mode(&timing,
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edid_ctrl->init_data.ds_data,
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video_format);
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u32 supported = timing.supported;
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u32 supported = hdmi_edid_is_mode_supported(edid_ctrl, &timing);
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struct hdmi_edid_sink_data *sink = &edid_ctrl->sink_data;
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if (video_format >= HDMI_VFRMT_MAX) {
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@ -1315,7 +1330,7 @@ static void hdmi_edid_add_sink_video_format(struct hdmi_edid_ctrl *edid_ctrl,
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u32 ret = hdmi_get_supported_mode(&timing,
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edid_ctrl->init_data.ds_data,
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video_format);
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u32 supported = timing.supported;
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u32 supported = hdmi_edid_is_mode_supported(edid_ctrl, &timing);
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struct hdmi_edid_sink_data *sink_data = &edid_ctrl->sink_data;
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struct disp_mode_info *disp_mode_list = sink_data->disp_mode_list;
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@ -2153,7 +2168,7 @@ void hdmi_edid_deinit(void *input)
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}
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} /* hdmi_edid_deinit */
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void *hdmi_edid_init(struct hdmi_edid_init_data *init_data)
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void *hdmi_edid_init(struct hdmi_edid_init_data *init_data, u32 max_pclk_khz)
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{
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struct hdmi_edid_ctrl *edid_ctrl = NULL;
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@ -2172,6 +2187,7 @@ void *hdmi_edid_init(struct hdmi_edid_init_data *init_data)
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edid_ctrl->init_data = *init_data;
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edid_ctrl->sink_mode = false;
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edid_ctrl->max_pclk_khz = max_pclk_khz;
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if (sysfs_create_group(init_data->sysfs_kobj,
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&hdmi_edid_fs_attrs_group)) {
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@ -33,6 +33,6 @@ int hdmi_edid_get_audio_blk(void *edid_ctrl,
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struct msm_hdmi_audio_edid_blk *blk);
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void hdmi_edid_set_video_resolution(void *edid_ctrl, u32 resolution);
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void hdmi_edid_deinit(void *edid_ctrl);
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void *hdmi_edid_init(struct hdmi_edid_init_data *init_data);
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void *hdmi_edid_init(struct hdmi_edid_init_data *init_data, u32 max_pclk_khz);
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#endif /* __HDMI_EDID_H__ */
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@ -75,6 +75,14 @@
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#define HDMI_TX_KHZ_TO_HZ 1000
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#define HDMI_TX_MHZ_TO_HZ 1000000
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/* Maximum pixel clock rates for hdmi tx */
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#define HDMI_DEFAULT_MAX_PCLK_RATE 148500
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#define HDMI_TX_3_MAX_PCLK_RATE 297000
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#define HDMI_TX_4_MAX_PCLK_RATE 600000
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#define HDMI_TX_VERSION_4 4
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#define HDMI_TX_VERSION_3 3
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/* Enable HDCP by default */
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static bool hdcp_feature_on = true;
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@ -277,6 +285,18 @@ static int hdmi_tx_get_version(struct hdmi_tx_ctrl *hdmi_ctrl)
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reg_val = (reg_val & 0xF0000000) >> 28;
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hdmi_ctrl->hdmi_tx_ver = reg_val;
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switch (hdmi_ctrl->hdmi_tx_ver) {
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case (HDMI_TX_VERSION_3):
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hdmi_ctrl->max_pclk_khz = HDMI_TX_3_MAX_PCLK_RATE;
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break;
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case (HDMI_TX_VERSION_4):
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hdmi_ctrl->max_pclk_khz = HDMI_TX_4_MAX_PCLK_RATE;
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break;
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default:
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hdmi_ctrl->max_pclk_khz = HDMI_DEFAULT_MAX_PCLK_RATE;
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break;
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}
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rc = hdmi_tx_enable_power(hdmi_ctrl, HDMI_TX_HPD_PM, false);
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if (rc) {
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DEV_ERR("%s: FAILED to disable power\n", __func__);
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@ -1167,7 +1187,7 @@ static int hdmi_tx_init_features(struct hdmi_tx_ctrl *hdmi_ctrl)
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edid_init_data.ds_data = &hdmi_ctrl->ds_data;
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hdmi_ctrl->feature_data[HDMI_TX_FEAT_EDID] =
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hdmi_edid_init(&edid_init_data);
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hdmi_edid_init(&edid_init_data, hdmi_ctrl->max_pclk_khz);
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if (!hdmi_ctrl->feature_data[HDMI_TX_FEAT_EDID]) {
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DEV_ERR("%s: hdmi_edid_init failed\n", __func__);
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return -EPERM;
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@ -1762,16 +1782,16 @@ void hdmi_tx_set_vendor_specific_infoframe(
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hdmi_video_format = 0x1;
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switch (hdmi_ctrl->vid_cfg.vic) {
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case HDMI_VFRMT_3840x2160p30_16_9:
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case HDMI_EVFRMT_3840x2160p30_16_9:
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hdmi_vic = 0x1;
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break;
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case HDMI_VFRMT_3840x2160p25_16_9:
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case HDMI_EVFRMT_3840x2160p25_16_9:
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hdmi_vic = 0x2;
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break;
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case HDMI_VFRMT_3840x2160p24_16_9:
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case HDMI_EVFRMT_3840x2160p24_16_9:
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hdmi_vic = 0x3;
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break;
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case HDMI_VFRMT_4096x2160p24_16_9:
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case HDMI_EVFRMT_4096x2160p24_16_9:
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hdmi_vic = 0x4;
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break;
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default:
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@ -126,6 +126,7 @@ struct hdmi_video_config {
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struct hdmi_tx_ctrl {
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struct platform_device *pdev;
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u32 hdmi_tx_ver;
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u32 max_pclk_khz;
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struct hdmi_tx_platform_data pdata;
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struct mdss_panel_data panel_data;
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struct mdss_util_intf *mdss_util;
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@ -181,17 +181,17 @@ int msm_hdmi_get_timing_info(
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case HDMI_VFRMT_1920x1080p30_16_9:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1920x1080p30_16_9);
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break;
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case HDMI_VFRMT_3840x2160p30_16_9:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p30_16_9);
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case HDMI_EVFRMT_3840x2160p30_16_9:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_EVFRMT_3840x2160p30_16_9);
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break;
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case HDMI_VFRMT_3840x2160p25_16_9:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p25_16_9);
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case HDMI_EVFRMT_3840x2160p25_16_9:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_EVFRMT_3840x2160p25_16_9);
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break;
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case HDMI_VFRMT_3840x2160p24_16_9:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p24_16_9);
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case HDMI_EVFRMT_3840x2160p24_16_9:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_EVFRMT_3840x2160p24_16_9);
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break;
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case HDMI_VFRMT_4096x2160p24_16_9:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_4096x2160p24_16_9);
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case HDMI_EVFRMT_4096x2160p24_16_9:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_EVFRMT_4096x2160p24_16_9);
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break;
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case HDMI_VFRMT_1024x768p60_4_3:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1024x768p60_4_3);
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@ -235,6 +235,56 @@ int msm_hdmi_get_timing_info(
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case HDMI_VFRMT_1280x800p60_16_10:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_1280x800p60_16_10);
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break;
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case HDMI_VFRMT_3840x2160p24_16_9:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p24_16_9);
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break;
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case HDMI_VFRMT_3840x2160p25_16_9:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p25_16_9);
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break;
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case HDMI_VFRMT_3840x2160p30_16_9:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p30_16_9);
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break;
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case HDMI_VFRMT_3840x2160p50_16_9:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p50_16_9);
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break;
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case HDMI_VFRMT_3840x2160p60_16_9:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p60_16_9);
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break;
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case HDMI_VFRMT_4096x2160p24_256_135:
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MSM_HDMI_MODES_GET_DETAILS(mode,
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HDMI_VFRMT_4096x2160p24_256_135);
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break;
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case HDMI_VFRMT_4096x2160p25_256_135:
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MSM_HDMI_MODES_GET_DETAILS(mode,
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HDMI_VFRMT_4096x2160p25_256_135);
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break;
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case HDMI_VFRMT_4096x2160p30_256_135:
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MSM_HDMI_MODES_GET_DETAILS(mode,
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HDMI_VFRMT_4096x2160p30_256_135);
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break;
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case HDMI_VFRMT_4096x2160p50_256_135:
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MSM_HDMI_MODES_GET_DETAILS(mode,
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HDMI_VFRMT_4096x2160p50_256_135);
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break;
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case HDMI_VFRMT_4096x2160p60_256_135:
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MSM_HDMI_MODES_GET_DETAILS(mode,
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HDMI_VFRMT_4096x2160p60_256_135);
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break;
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case HDMI_VFRMT_3840x2160p24_64_27:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p24_64_27);
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break;
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case HDMI_VFRMT_3840x2160p25_64_27:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p25_64_27);
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break;
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case HDMI_VFRMT_3840x2160p30_64_27:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p30_64_27);
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break;
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case HDMI_VFRMT_3840x2160p50_64_27:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p50_64_27);
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break;
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case HDMI_VFRMT_3840x2160p60_64_27:
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MSM_HDMI_MODES_GET_DETAILS(mode, HDMI_VFRMT_3840x2160p60_64_27);
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break;
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default:
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ret = hdmi_get_resv_timing_info(mode, id);
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}
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@ -324,6 +324,26 @@ struct hdmi_util_ds_data {
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u32 ds_max_clk;
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};
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static inline int hdmi_tx_get_v_total(const struct msm_hdmi_mode_timing_info *t)
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{
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if (t) {
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return t->active_v + t->front_porch_v + t->pulse_width_v +
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t->back_porch_v;
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}
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return 0;
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}
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static inline int hdmi_tx_get_h_total(const struct msm_hdmi_mode_timing_info *t)
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{
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if (t) {
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return t->active_h + t->front_porch_h + t->pulse_width_h +
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t->back_porch_h;
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}
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return 0;
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}
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/* video timing related utility routines */
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int hdmi_get_video_id_code(struct msm_hdmi_mode_timing_info *timing_in,
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struct hdmi_util_ds_data *ds_data);
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@ -3,12 +3,17 @@
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#include <linux/types.h>
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#include <linux/errno.h>
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#define MSM_HDMI_RGB_888_24BPP_FORMAT BIT(0)
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#define MSM_HDMI_YUV_420_12BPP_FORMAT BIT(1)
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enum aspect_ratio {
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HDMI_RES_AR_INVALID,
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HDMI_RES_AR_4_3,
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HDMI_RES_AR_5_4,
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HDMI_RES_AR_16_9,
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HDMI_RES_AR_16_10,
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HDMI_RES_AR_64_27,
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HDMI_RES_AR_256_135,
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HDMI_RES_AR_MAX,
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};
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@ -31,6 +36,8 @@ struct msm_hdmi_mode_timing_info {
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uint32_t interlaced;
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uint32_t supported;
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enum aspect_ratio ar;
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/* Flags indicating support for specific pixel formats */
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uint32_t pixel_formats;
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};
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#define MSM_HDMI_INIT_RES_PAGE 1
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@ -124,17 +131,61 @@ struct msm_hdmi_mode_timing_info {
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#define HDMI_VFRMT_1280x720p30_16_9 62
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#define HDMI_VFRMT_1920x1080p120_16_9 63
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#define HDMI_VFRMT_1920x1080p100_16_9 64
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/* Video Identification Codes from 65-127 are reserved for the future */
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#define HDMI_VFRMT_1280x720p24_64_27 65
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#define HDMI_VFRMT_1280x720p25_64_27 66
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#define HDMI_VFRMT_1280x720p30_64_27 67
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#define HDMI_VFRMT_1280x720p50_64_27 68
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#define HDMI_VFRMT_1280x720p60_64_27 69
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#define HDMI_VFRMT_1280x720p100_64_27 70
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#define HDMI_VFRMT_1280x720p120_64_27 71
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#define HDMI_VFRMT_1920x1080p24_64_27 72
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#define HDMI_VFRMT_1920x1080p25_64_27 73
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#define HDMI_VFRMT_1920x1080p30_64_27 74
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#define HDMI_VFRMT_1920x1080p50_64_27 75
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#define HDMI_VFRMT_1920x1080p60_64_27 76
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#define HDMI_VFRMT_1920x1080p100_64_27 77
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#define HDMI_VFRMT_1920x1080p120_64_27 78
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#define HDMI_VFRMT_1680x720p24_64_27 79
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#define HDMI_VFRMT_1680x720p25_64_27 80
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#define HDMI_VFRMT_1680x720p30_64_27 81
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#define HDMI_VFRMT_1680x720p50_64_27 82
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#define HDMI_VFRMT_1680x720p60_64_27 83
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#define HDMI_VFRMT_1680x720p100_64_27 84
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#define HDMI_VFRMT_1680x720p120_64_27 85
|
||||
#define HDMI_VFRMT_2560x1080p24_64_27 86
|
||||
#define HDMI_VFRMT_2560x1080p25_64_27 87
|
||||
#define HDMI_VFRMT_2560x1080p30_64_27 88
|
||||
#define HDMI_VFRMT_2560x1080p50_64_27 89
|
||||
#define HDMI_VFRMT_2560x1080p60_64_27 90
|
||||
#define HDMI_VFRMT_2560x1080p100_64_27 91
|
||||
#define HDMI_VFRMT_2560x1080p120_64_27 92
|
||||
#define HDMI_VFRMT_3840x2160p24_16_9 93
|
||||
#define HDMI_VFRMT_3840x2160p25_16_9 94
|
||||
#define HDMI_VFRMT_3840x2160p30_16_9 95
|
||||
#define HDMI_VFRMT_3840x2160p50_16_9 96
|
||||
#define HDMI_VFRMT_3840x2160p60_16_9 97
|
||||
#define HDMI_VFRMT_4096x2160p24_256_135 98
|
||||
#define HDMI_VFRMT_4096x2160p25_256_135 99
|
||||
#define HDMI_VFRMT_4096x2160p30_256_135 100
|
||||
#define HDMI_VFRMT_4096x2160p50_256_135 101
|
||||
#define HDMI_VFRMT_4096x2160p60_256_135 102
|
||||
#define HDMI_VFRMT_3840x2160p24_64_27 103
|
||||
#define HDMI_VFRMT_3840x2160p25_64_27 104
|
||||
#define HDMI_VFRMT_3840x2160p30_64_27 105
|
||||
#define HDMI_VFRMT_3840x2160p50_64_27 106
|
||||
#define HDMI_VFRMT_3840x2160p60_64_27 107
|
||||
|
||||
/* Video Identification Codes from 107-127 are reserved for the future */
|
||||
#define HDMI_VFRMT_END 127
|
||||
|
||||
#define EVFRMT_OFF(x) (HDMI_VFRMT_END + x)
|
||||
|
||||
/* extended video formats */
|
||||
#define HDMI_VFRMT_3840x2160p30_16_9 EVFRMT_OFF(1)
|
||||
#define HDMI_VFRMT_3840x2160p25_16_9 EVFRMT_OFF(2)
|
||||
#define HDMI_VFRMT_3840x2160p24_16_9 EVFRMT_OFF(3)
|
||||
#define HDMI_VFRMT_4096x2160p24_16_9 EVFRMT_OFF(4)
|
||||
#define HDMI_EVFRMT_END HDMI_VFRMT_4096x2160p24_16_9
|
||||
#define HDMI_EVFRMT_3840x2160p30_16_9 EVFRMT_OFF(1)
|
||||
#define HDMI_EVFRMT_3840x2160p25_16_9 EVFRMT_OFF(2)
|
||||
#define HDMI_EVFRMT_3840x2160p24_16_9 EVFRMT_OFF(3)
|
||||
#define HDMI_EVFRMT_4096x2160p24_16_9 EVFRMT_OFF(4)
|
||||
#define HDMI_EVFRMT_END HDMI_EVFRMT_4096x2160p24_16_9
|
||||
|
||||
#define WQXGA_OFF(x) (HDMI_EVFRMT_END + x)
|
||||
|
||||
|
|
@ -196,110 +247,176 @@ struct msm_hdmi_mode_timing_info {
|
|||
|
||||
#define HDMI_VFRMT_640x480p60_4_3_TIMING \
|
||||
{HDMI_VFRMT_640x480p60_4_3, 640, 16, 96, 48, true, \
|
||||
480, 10, 2, 33, true, 25200, 60000, false, true, HDMI_RES_AR_4_3}
|
||||
480, 10, 2, 33, true, 25200, 60000, false, true, HDMI_RES_AR_4_3, 0}
|
||||
#define HDMI_VFRMT_720x480p60_4_3_TIMING \
|
||||
{HDMI_VFRMT_720x480p60_4_3, 720, 16, 62, 60, true, \
|
||||
480, 9, 6, 30, true, 27027, 60000, false, true, HDMI_RES_AR_4_3}
|
||||
480, 9, 6, 30, true, 27027, 60000, false, true, HDMI_RES_AR_4_3, 0}
|
||||
#define HDMI_VFRMT_720x480p60_16_9_TIMING \
|
||||
{HDMI_VFRMT_720x480p60_16_9, 720, 16, 62, 60, true, \
|
||||
480, 9, 6, 30, true, 27027, 60000, false, true, HDMI_RES_AR_16_9}
|
||||
480, 9, 6, 30, true, 27027, 60000, false, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_1280x720p60_16_9_TIMING \
|
||||
{HDMI_VFRMT_1280x720p60_16_9, 1280, 110, 40, 220, false, \
|
||||
720, 5, 5, 20, false, 74250, 60000, false, true, HDMI_RES_AR_16_9}
|
||||
720, 5, 5, 20, false, 74250, 60000, false, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_1920x1080i60_16_9_TIMING \
|
||||
{HDMI_VFRMT_1920x1080i60_16_9, 1920, 88, 44, 148, false, \
|
||||
540, 2, 5, 5, false, 74250, 60000, false, true, HDMI_RES_AR_16_9}
|
||||
540, 2, 5, 5, false, 74250, 60000, false, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_1440x480i60_4_3_TIMING \
|
||||
{HDMI_VFRMT_1440x480i60_4_3, 1440, 38, 124, 114, true, \
|
||||
240, 4, 3, 15, true, 27000, 60000, true, true, HDMI_RES_AR_4_3}
|
||||
240, 4, 3, 15, true, 27000, 60000, true, true, HDMI_RES_AR_4_3, 0}
|
||||
#define HDMI_VFRMT_1440x480i60_16_9_TIMING \
|
||||
{HDMI_VFRMT_1440x480i60_16_9, 1440, 38, 124, 114, true, \
|
||||
240, 4, 3, 15, true, 27000, 60000, true, true, HDMI_RES_AR_16_9}
|
||||
240, 4, 3, 15, true, 27000, 60000, true, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_1920x1080p60_16_9_TIMING \
|
||||
{HDMI_VFRMT_1920x1080p60_16_9, 1920, 88, 44, 148, false, \
|
||||
1080, 4, 5, 36, false, 148500, 60000, false, true, HDMI_RES_AR_16_9}
|
||||
1080, 4, 5, 36, false, 148500, 60000, false, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_720x576p50_4_3_TIMING \
|
||||
{HDMI_VFRMT_720x576p50_4_3, 720, 12, 64, 68, true, \
|
||||
576, 5, 5, 39, true, 27000, 50000, false, true, HDMI_RES_AR_4_3}
|
||||
576, 5, 5, 39, true, 27000, 50000, false, true, HDMI_RES_AR_4_3, 0}
|
||||
#define HDMI_VFRMT_720x576p50_16_9_TIMING \
|
||||
{HDMI_VFRMT_720x576p50_16_9, 720, 12, 64, 68, true, \
|
||||
576, 5, 5, 39, true, 27000, 50000, false, true, HDMI_RES_AR_16_9}
|
||||
576, 5, 5, 39, true, 27000, 50000, false, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_1280x720p50_16_9_TIMING \
|
||||
{HDMI_VFRMT_1280x720p50_16_9, 1280, 440, 40, 220, false, \
|
||||
720, 5, 5, 20, false, 74250, 50000, false, true, HDMI_RES_AR_16_9}
|
||||
720, 5, 5, 20, false, 74250, 50000, false, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_1440x576i50_4_3_TIMING \
|
||||
{HDMI_VFRMT_1440x576i50_4_3, 1440, 24, 126, 138, true, \
|
||||
288, 2, 3, 19, true, 27000, 50000, true, true, HDMI_RES_AR_4_3}
|
||||
288, 2, 3, 19, true, 27000, 50000, true, true, HDMI_RES_AR_4_3, 0}
|
||||
#define HDMI_VFRMT_1440x576i50_16_9_TIMING \
|
||||
{HDMI_VFRMT_1440x576i50_16_9, 1440, 24, 126, 138, true, \
|
||||
288, 2, 3, 19, true, 27000, 50000, true, true, HDMI_RES_AR_16_9}
|
||||
288, 2, 3, 19, true, 27000, 50000, true, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_1920x1080p50_16_9_TIMING \
|
||||
{HDMI_VFRMT_1920x1080p50_16_9, 1920, 528, 44, 148, false, \
|
||||
1080, 4, 5, 36, false, 148500, 50000, false, true, HDMI_RES_AR_16_9}
|
||||
1080, 4, 5, 36, false, 148500, 50000, false, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_1920x1080p24_16_9_TIMING \
|
||||
{HDMI_VFRMT_1920x1080p24_16_9, 1920, 638, 44, 148, false, \
|
||||
1080, 4, 5, 36, false, 74250, 24000, false, true, HDMI_RES_AR_16_9}
|
||||
1080, 4, 5, 36, false, 74250, 24000, false, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_1920x1080p25_16_9_TIMING \
|
||||
{HDMI_VFRMT_1920x1080p25_16_9, 1920, 528, 44, 148, false, \
|
||||
1080, 4, 5, 36, false, 74250, 25000, false, true, HDMI_RES_AR_16_9}
|
||||
1080, 4, 5, 36, false, 74250, 25000, false, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_1920x1080p30_16_9_TIMING \
|
||||
{HDMI_VFRMT_1920x1080p30_16_9, 1920, 88, 44, 148, false, \
|
||||
1080, 4, 5, 36, false, 74250, 30000, false, true, HDMI_RES_AR_16_9}
|
||||
1080, 4, 5, 36, false, 74250, 30000, false, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_1024x768p60_4_3_TIMING \
|
||||
{HDMI_VFRMT_1024x768p60_4_3, 1024, 24, 136, 160, false, \
|
||||
768, 2, 6, 29, false, 65000, 60000, false, true, HDMI_RES_AR_4_3}
|
||||
768, 2, 6, 29, false, 65000, 60000, false, true, HDMI_RES_AR_4_3, 0}
|
||||
#define HDMI_VFRMT_1280x1024p60_5_4_TIMING \
|
||||
{HDMI_VFRMT_1280x1024p60_5_4, 1280, 48, 112, 248, false, \
|
||||
1024, 1, 3, 38, false, 108000, 60000, false, true, HDMI_RES_AR_5_4}
|
||||
1024, 1, 3, 38, false, 108000, 60000, false, true, HDMI_RES_AR_5_4, 0}
|
||||
#define HDMI_VFRMT_2560x1600p60_16_9_TIMING \
|
||||
{HDMI_VFRMT_2560x1600p60_16_9, 2560, 48, 32, 80, false, \
|
||||
1600, 3, 6, 37, false, 268500, 60000, false, true, HDMI_RES_AR_16_9}
|
||||
#define HDMI_VFRMT_3840x2160p30_16_9_TIMING \
|
||||
{HDMI_VFRMT_3840x2160p30_16_9, 3840, 176, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 30000, false, true, HDMI_RES_AR_16_9}
|
||||
#define HDMI_VFRMT_3840x2160p25_16_9_TIMING \
|
||||
{HDMI_VFRMT_3840x2160p25_16_9, 3840, 1056, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 25000, false, true, HDMI_RES_AR_16_9}
|
||||
#define HDMI_VFRMT_3840x2160p24_16_9_TIMING \
|
||||
{HDMI_VFRMT_3840x2160p24_16_9, 3840, 1276, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 24000, false, true, HDMI_RES_AR_16_9}
|
||||
#define HDMI_VFRMT_4096x2160p24_16_9_TIMING \
|
||||
{HDMI_VFRMT_4096x2160p24_16_9, 4096, 1020, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 24000, false, true, HDMI_RES_AR_16_9}
|
||||
1600, 3, 6, 37, false, 268500, 60000, false, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_EVFRMT_3840x2160p30_16_9_TIMING \
|
||||
{HDMI_EVFRMT_3840x2160p30_16_9, 3840, 176, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 30000, false, true, \
|
||||
HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_EVFRMT_3840x2160p25_16_9_TIMING \
|
||||
{HDMI_EVFRMT_3840x2160p25_16_9, 3840, 1056, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 25000, false, true, \
|
||||
HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_EVFRMT_3840x2160p24_16_9_TIMING \
|
||||
{HDMI_EVFRMT_3840x2160p24_16_9, 3840, 1276, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 24000, false, true, \
|
||||
HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_EVFRMT_4096x2160p24_16_9_TIMING \
|
||||
{HDMI_EVFRMT_4096x2160p24_16_9, 4096, 1020, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 24000, false, true, \
|
||||
HDMI_RES_AR_16_9, 0}
|
||||
|
||||
#define HDMI_VFRMT_800x600p60_4_3_TIMING \
|
||||
{HDMI_VFRMT_800x600p60_4_3, 800, 40, 128, 88, false, \
|
||||
600, 1, 4, 23, false, 40000, 60000, false, true, HDMI_RES_AR_4_3}
|
||||
600, 1, 4, 23, false, 40000, 60000, false, true, HDMI_RES_AR_4_3, 0}
|
||||
#define HDMI_VFRMT_848x480p60_16_9_TIMING \
|
||||
{HDMI_VFRMT_848x480p60_16_9, 848, 16, 112, 112, false, \
|
||||
480, 6, 8, 23, false, 33750, 60000, false, true, HDMI_RES_AR_16_9}
|
||||
480, 6, 8, 23, false, 33750, 60000, false, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_1280x960p60_4_3_TIMING\
|
||||
{HDMI_VFRMT_1280x960p60_4_3, 1280, 96, 112, 312, false, \
|
||||
960, 1, 3, 36, false, 108000, 60000, false, true, HDMI_RES_AR_4_3}
|
||||
960, 1, 3, 36, false, 108000, 60000, false, true, HDMI_RES_AR_4_3, 0}
|
||||
#define HDMI_VFRMT_1360x768p60_16_9_TIMING\
|
||||
{HDMI_VFRMT_1360x768p60_16_9, 1360, 64, 112, 256, false, \
|
||||
768, 3, 6, 18, false, 85500, 60000, false, true, HDMI_RES_AR_16_9}
|
||||
768, 3, 6, 18, false, 85500, 60000, false, true, HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_1440x900p60_16_10_TIMING\
|
||||
{HDMI_VFRMT_1440x900p60_16_10, 1440, 48, 32, 80, false, \
|
||||
900, 3, 6, 17, true, 88750, 60000, false, true, HDMI_RES_AR_16_10}
|
||||
900, 3, 6, 17, true, 88750, 60000, false, true, HDMI_RES_AR_16_10, 0}
|
||||
#define HDMI_VFRMT_1400x1050p60_4_3_TIMING\
|
||||
{HDMI_VFRMT_1400x1050p60_4_3, 1400, 48, 32, 80, false, \
|
||||
1050, 3, 4, 23, true, 101000, 60000, false, true, HDMI_RES_AR_4_3}
|
||||
1050, 3, 4, 23, true, 101000, 60000, false, true, HDMI_RES_AR_4_3, 0}
|
||||
#define HDMI_VFRMT_1680x1050p60_16_10_TIMING\
|
||||
{HDMI_VFRMT_1680x1050p60_16_10, 1680, 48, 32, 80, false, \
|
||||
1050, 3, 6, 21, true, 119000, 60000, false, true, HDMI_RES_AR_16_10}
|
||||
1050, 3, 6, 21, true, 119000, 60000, false, true, HDMI_RES_AR_16_10, 0}
|
||||
#define HDMI_VFRMT_1600x1200p60_4_3_TIMING\
|
||||
{HDMI_VFRMT_1600x1200p60_4_3, 1600, 64, 192, 304, false, \
|
||||
1200, 1, 3, 46, false, 162000, 60000, false, true, HDMI_RES_AR_4_3}
|
||||
1200, 1, 3, 46, false, 162000, 60000, false, true, HDMI_RES_AR_4_3, 0}
|
||||
#define HDMI_VFRMT_1920x1200p60_16_10_TIMING\
|
||||
{HDMI_VFRMT_1920x1200p60_16_10, 1920, 48, 32, 80, false,\
|
||||
1200, 3, 6, 26, true, 154000, 60000, false, true, HDMI_RES_AR_16_10}
|
||||
1200, 3, 6, 26, true, 154000, 60000, false, true, HDMI_RES_AR_16_10, 0}
|
||||
#define HDMI_VFRMT_1366x768p60_16_10_TIMING\
|
||||
{HDMI_VFRMT_1366x768p60_16_10, 1366, 70, 143, 213, false,\
|
||||
768, 3, 3, 24, false, 85500, 60000, false, true, HDMI_RES_AR_16_10}
|
||||
768, 3, 3, 24, false, 85500, 60000, false, true, HDMI_RES_AR_16_10, 0}
|
||||
#define HDMI_VFRMT_1280x800p60_16_10_TIMING\
|
||||
{HDMI_VFRMT_1280x800p60_16_10, 1280, 72, 128, 200, true,\
|
||||
800, 3, 6, 22, false, 83500, 60000, false, true, HDMI_RES_AR_16_10}
|
||||
800, 3, 6, 22, false, 83500, 60000, false, true, HDMI_RES_AR_16_10, 0}
|
||||
#define HDMI_VFRMT_3840x2160p24_16_9_TIMING \
|
||||
{HDMI_VFRMT_3840x2160p24_16_9, 3840, 1276, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 24000, false, true, \
|
||||
HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_3840x2160p25_16_9_TIMING \
|
||||
{HDMI_VFRMT_3840x2160p25_16_9, 3840, 1056, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 25000, false, true, \
|
||||
HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_3840x2160p30_16_9_TIMING \
|
||||
{HDMI_VFRMT_3840x2160p30_16_9, 3840, 176, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 30000, false, true, \
|
||||
HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_3840x2160p50_16_9_TIMING \
|
||||
{HDMI_VFRMT_3840x2160p50_16_9, 3840, 1056, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 594000, 50000, false, true, \
|
||||
HDMI_RES_AR_16_9, 0}
|
||||
#define HDMI_VFRMT_3840x2160p60_16_9_TIMING \
|
||||
{HDMI_VFRMT_3840x2160p60_16_9, 3840, 176, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 594000, 60000, false, true, \
|
||||
HDMI_RES_AR_16_9, 0}
|
||||
|
||||
#define HDMI_VFRMT_4096x2160p24_256_135_TIMING \
|
||||
{HDMI_VFRMT_4096x2160p24_256_135, 4096, 1020, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 24000, false, true, \
|
||||
HDMI_RES_AR_256_135, 0}
|
||||
#define HDMI_VFRMT_4096x2160p25_256_135_TIMING \
|
||||
{HDMI_VFRMT_4096x2160p25_256_135, 4096, 968, 88, 128, false, \
|
||||
2160, 8, 10, 72, false, 297000, 25000, false, true, \
|
||||
HDMI_RES_AR_256_135, 0}
|
||||
#define HDMI_VFRMT_4096x2160p30_256_135_TIMING \
|
||||
{HDMI_VFRMT_4096x2160p30_256_135, 4096, 88, 88, 128, false, \
|
||||
2160, 8, 10, 72, false, 297000, 30000, false, true, \
|
||||
HDMI_RES_AR_256_135, 0}
|
||||
#define HDMI_VFRMT_4096x2160p50_256_135_TIMING \
|
||||
{HDMI_VFRMT_4096x2160p50_256_135, 4096, 968, 88, 128, false, \
|
||||
2160, 8, 10, 72, false, 594000, 50000, false, true, \
|
||||
HDMI_RES_AR_256_135, 0}
|
||||
#define HDMI_VFRMT_4096x2160p60_256_135_TIMING \
|
||||
{HDMI_VFRMT_4096x2160p60_256_135, 4096, 88, 88, 128, false, \
|
||||
2160, 8, 10, 72, false, 594000, 60000, false, true, \
|
||||
HDMI_RES_AR_256_135, 0}
|
||||
|
||||
#define HDMI_VFRMT_3840x2160p24_64_27_TIMING \
|
||||
{HDMI_VFRMT_3840x2160p24_64_27, 3840, 1276, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 24000, false, true, \
|
||||
HDMI_RES_AR_64_27, 0}
|
||||
#define HDMI_VFRMT_3840x2160p25_64_27_TIMING \
|
||||
{HDMI_VFRMT_3840x2160p25_64_27, 3840, 1056, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 25000, false, true, \
|
||||
HDMI_RES_AR_64_27, 0}
|
||||
#define HDMI_VFRMT_3840x2160p30_64_27_TIMING \
|
||||
{HDMI_VFRMT_3840x2160p30_64_27, 3840, 176, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 297000, 30000, false, true, \
|
||||
HDMI_RES_AR_64_27, 0}
|
||||
#define HDMI_VFRMT_3840x2160p50_64_27_TIMING \
|
||||
{HDMI_VFRMT_3840x2160p50_64_27, 3840, 1056, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 594000, 50000, false, true, \
|
||||
HDMI_RES_AR_64_27, 0}
|
||||
#define HDMI_VFRMT_3840x2160p60_64_27_TIMING \
|
||||
{HDMI_VFRMT_3840x2160p60_64_27, 3840, 176, 88, 296, false, \
|
||||
2160, 8, 10, 72, false, 594000, 60000, false, true, \
|
||||
HDMI_RES_AR_64_27, 0}
|
||||
|
||||
#define MSM_HDMI_MODES_SET_TIMING(LUT, MODE) do { \
|
||||
struct msm_hdmi_mode_timing_info mode = MODE##_TIMING; \
|
||||
|
|
@ -353,16 +470,46 @@ do { \
|
|||
HDMI_VFRMT_1920x1080p25_16_9); \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_1920x1080p30_16_9); \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_3840x2160p24_16_9); \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_3840x2160p25_16_9); \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_3840x2160p30_16_9); \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_3840x2160p50_16_9); \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_3840x2160p60_16_9); \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_4096x2160p24_256_135);\
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_4096x2160p25_256_135);\
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_4096x2160p30_256_135);\
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_4096x2160p50_256_135);\
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_4096x2160p60_256_135);\
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_3840x2160p24_64_27); \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_3840x2160p25_64_27); \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_3840x2160p30_64_27); \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_3840x2160p50_64_27); \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_3840x2160p60_64_27); \
|
||||
} \
|
||||
if (__type & MSM_HDMI_MODES_XTND) { \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_3840x2160p30_16_9); \
|
||||
HDMI_EVFRMT_3840x2160p30_16_9); \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_3840x2160p25_16_9); \
|
||||
HDMI_EVFRMT_3840x2160p25_16_9); \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_3840x2160p24_16_9); \
|
||||
HDMI_EVFRMT_3840x2160p24_16_9); \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
HDMI_VFRMT_4096x2160p24_16_9); \
|
||||
HDMI_EVFRMT_4096x2160p24_16_9); \
|
||||
} \
|
||||
if (__type & MSM_HDMI_MODES_DVI) { \
|
||||
MSM_HDMI_MODES_SET_TIMING(__lut, \
|
||||
|
|
@ -401,24 +548,4 @@ do { \
|
|||
*mode = info; \
|
||||
} while (0)
|
||||
|
||||
|
||||
static inline int hdmi_tx_get_v_total(const struct msm_hdmi_mode_timing_info *t)
|
||||
{
|
||||
if (t) {
|
||||
return t->active_v + t->front_porch_v + t->pulse_width_v +
|
||||
t->back_porch_v;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int hdmi_tx_get_h_total(const struct msm_hdmi_mode_timing_info *t)
|
||||
{
|
||||
if (t) {
|
||||
return t->active_h + t->front_porch_h + t->pulse_width_h +
|
||||
t->back_porch_h;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* _UAPI_MSM_HDMI_MODES_H__ */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue