Merge "fg-memif: update IMA error handling and clear sequence"
This commit is contained in:
commit
dd4dc008b8
4 changed files with 213 additions and 39 deletions
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@ -342,6 +342,8 @@ extern int fg_read(struct fg_chip *chip, int addr, u8 *val, int len);
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extern int fg_write(struct fg_chip *chip, int addr, u8 *val, int len);
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extern int fg_masked_write(struct fg_chip *chip, int addr, u8 mask, u8 val);
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extern int fg_ima_init(struct fg_chip *chip);
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extern int fg_clear_ima_errors_if_any(struct fg_chip *chip, bool check_hw_sts);
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extern int fg_clear_dma_errors_if_any(struct fg_chip *chip);
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extern int fg_debugfs_create(struct fg_chip *chip);
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extern void fill_string(char *str, size_t str_len, u8 *buf, int buf_len);
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extern int64_t twos_compliment_extend(int64_t val, int s_bit_pos);
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@ -64,44 +64,90 @@ static int fg_config_access_mode(struct fg_chip *chip, bool access, bool burst)
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static int fg_run_iacs_clear_sequence(struct fg_chip *chip)
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{
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u8 tmp;
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int rc;
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u8 val, hw_sts, exp_sts;
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int rc, tries = 250;
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/*
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* Values to write for running IACS clear sequence comes from
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* hardware documentation.
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*/
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rc = fg_masked_write(chip, MEM_IF_IMA_CFG(chip), IACS_CLR_BIT,
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IACS_CLR_BIT);
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rc = fg_masked_write(chip, MEM_IF_IMA_CFG(chip),
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IACS_CLR_BIT | STATIC_CLK_EN_BIT,
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IACS_CLR_BIT | STATIC_CLK_EN_BIT);
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if (rc < 0) {
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pr_err("failed to write 0x%04x, rc=%d\n", MEM_IF_IMA_CFG(chip),
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rc);
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return rc;
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}
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tmp = 0x4;
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rc = fg_write(chip, MEM_IF_ADDR_MSB(chip), &tmp, 1);
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rc = fg_config_access_mode(chip, FG_READ, false);
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if (rc < 0) {
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pr_err("failed to write 0x%04x, rc=%d\n", MEM_IF_ADDR_LSB(chip),
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rc);
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pr_err("failed to write to 0x%04x, rc=%d\n",
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MEM_IF_IMA_CTL(chip), rc);
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return rc;
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}
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tmp = 0x0;
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rc = fg_write(chip, MEM_IF_WR_DATA3(chip), &tmp, 1);
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rc = fg_masked_write(chip, MEM_IF_MEM_INTF_CFG(chip),
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MEM_ACCESS_REQ_BIT | IACS_SLCT_BIT,
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MEM_ACCESS_REQ_BIT | IACS_SLCT_BIT);
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if (rc < 0) {
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pr_err("failed to write 0x%04x, rc=%d\n", MEM_IF_WR_DATA3(chip),
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rc);
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pr_err("failed to set ima_req_access bit rc=%d\n", rc);
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return rc;
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}
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rc = fg_read(chip, MEM_IF_RD_DATA3(chip), &tmp, 1);
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if (rc < 0) {
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pr_err("failed to read 0x%04x, rc=%d\n", MEM_IF_RD_DATA3(chip),
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rc);
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return rc;
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/* Delay for the clock to reach FG */
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usleep_range(35, 40);
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while (1) {
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val = 0;
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rc = fg_write(chip, MEM_IF_ADDR_MSB(chip), &val, 1);
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if (rc < 0) {
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pr_err("failed to write 0x%04x, rc=%d\n",
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MEM_IF_ADDR_MSB(chip), rc);
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return rc;
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}
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val = 0;
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rc = fg_write(chip, MEM_IF_WR_DATA3(chip), &val, 1);
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if (rc < 0) {
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pr_err("failed to write 0x%04x, rc=%d\n",
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MEM_IF_WR_DATA3(chip), rc);
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return rc;
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}
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rc = fg_read(chip, MEM_IF_RD_DATA3(chip), &val, 1);
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if (rc < 0) {
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pr_err("failed to read 0x%04x, rc=%d\n",
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MEM_IF_RD_DATA3(chip), rc);
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return rc;
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}
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/* Delay for IMA hardware to clear */
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usleep_range(35, 40);
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rc = fg_read(chip, MEM_IF_IMA_HW_STS(chip), &hw_sts, 1);
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if (rc < 0) {
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pr_err("failed to read ima_hw_sts rc=%d\n", rc);
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return rc;
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}
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if (hw_sts != 0)
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continue;
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rc = fg_read(chip, MEM_IF_IMA_EXP_STS(chip), &exp_sts, 1);
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if (rc < 0) {
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pr_err("failed to read ima_exp_sts rc=%d\n", rc);
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return rc;
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}
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if (exp_sts == 0 || !(--tries))
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break;
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}
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if (!tries)
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pr_err("Failed to clear the error? hw_sts: %x exp_sts: %d\n",
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hw_sts, exp_sts);
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rc = fg_masked_write(chip, MEM_IF_IMA_CFG(chip), IACS_CLR_BIT, 0);
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if (rc < 0) {
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pr_err("failed to write 0x%04x, rc=%d\n", MEM_IF_IMA_CFG(chip),
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@ -109,14 +155,65 @@ static int fg_run_iacs_clear_sequence(struct fg_chip *chip)
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return rc;
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}
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udelay(5);
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rc = fg_masked_write(chip, MEM_IF_MEM_INTF_CFG(chip),
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MEM_ACCESS_REQ_BIT | IACS_SLCT_BIT, 0);
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if (rc < 0) {
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pr_err("failed to write to 0x%04x, rc=%d\n",
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MEM_IF_MEM_INTF_CFG(chip), rc);
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return rc;
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}
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/* Delay before next transaction is attempted */
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usleep_range(35, 40);
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fg_dbg(chip, FG_SRAM_READ | FG_SRAM_WRITE, "IACS clear sequence complete\n");
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return rc;
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}
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static int fg_check_for_ima_errors(struct fg_chip *chip)
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int fg_clear_dma_errors_if_any(struct fg_chip *chip)
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{
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int rc;
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u8 dma_sts;
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rc = fg_read(chip, MEM_IF_DMA_STS(chip), &dma_sts, 1);
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if (rc < 0) {
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pr_err("failed to read addr=0x%04x, rc=%d\n",
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MEM_IF_DMA_STS(chip), rc);
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return rc;
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}
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fg_dbg(chip, FG_STATUS, "dma_sts: %x\n", dma_sts);
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if (dma_sts & (DMA_WRITE_ERROR_BIT | DMA_READ_ERROR_BIT)) {
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rc = fg_masked_write(chip, MEM_IF_DMA_CTL(chip),
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DMA_CLEAR_LOG_BIT, DMA_CLEAR_LOG_BIT);
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if (rc < 0) {
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pr_err("failed to write addr=0x%04x, rc=%d\n",
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MEM_IF_DMA_CTL(chip), rc);
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return rc;
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}
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}
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return 0;
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}
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int fg_clear_ima_errors_if_any(struct fg_chip *chip, bool check_hw_sts)
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{
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int rc = 0;
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u8 err_sts, exp_sts = 0, hw_sts = 0;
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bool run_err_clr_seq = false;
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rc = fg_read(chip, MEM_IF_IMA_EXP_STS(chip), &exp_sts, 1);
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if (rc < 0) {
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pr_err("failed to read ima_exp_sts rc=%d\n", rc);
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return rc;
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}
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rc = fg_read(chip, MEM_IF_IMA_HW_STS(chip), &hw_sts, 1);
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if (rc < 0) {
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pr_err("failed to read ima_hw_sts rc=%d\n", rc);
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return rc;
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}
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rc = fg_read(chip, MEM_IF_IMA_ERR_STS(chip), &err_sts, 1);
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if (rc < 0) {
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@ -124,22 +221,30 @@ static int fg_check_for_ima_errors(struct fg_chip *chip)
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return rc;
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}
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if (err_sts & (ADDR_STBL_ERR_BIT | WR_ACS_ERR_BIT | RD_ACS_ERR_BIT)) {
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rc = fg_read(chip, MEM_IF_IMA_EXP_STS(chip), &exp_sts, 1);
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if (rc < 0) {
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pr_err("failed to read ima_exp_sts rc=%d\n", rc);
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return rc;
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fg_dbg(chip, FG_STATUS, "ima_err_sts=%x ima_exp_sts=%x ima_hw_sts=%x\n",
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err_sts, exp_sts, hw_sts);
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if (check_hw_sts) {
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/*
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* Lower nibble should be equal to upper nibble before SRAM
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* transactions begins from SW side. If they are unequal, then
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* the error clear sequence should be run irrespective of IMA
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* exception errors.
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*/
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if ((hw_sts & 0x0F) != hw_sts >> 4) {
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pr_err("IMA HW not in correct state, hw_sts=%x\n",
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hw_sts);
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run_err_clr_seq = true;
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}
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}
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rc = fg_read(chip, MEM_IF_IMA_HW_STS(chip), &hw_sts, 1);
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if (rc < 0) {
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pr_err("failed to read ima_hw_sts rc=%d\n", rc);
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return rc;
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}
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pr_err("ima_err_sts=%x ima_exp_sts=%x ima_hw_sts=%x\n",
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err_sts, exp_sts, hw_sts);
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if (exp_sts & (IACS_ERR_BIT | XCT_TYPE_ERR_BIT | DATA_RD_ERR_BIT |
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DATA_WR_ERR_BIT | ADDR_BURST_WRAP_BIT | ADDR_STABLE_ERR_BIT)) {
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pr_err("IMA exception bit set, exp_sts=%x\n", exp_sts);
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run_err_clr_seq = true;
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}
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if (run_err_clr_seq) {
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/* clear the error */
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rc = fg_run_iacs_clear_sequence(chip);
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if (rc < 0) {
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@ -156,7 +261,7 @@ static int fg_check_for_ima_errors(struct fg_chip *chip)
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static int fg_check_iacs_ready(struct fg_chip *chip)
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{
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int rc = 0, timeout = 250;
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int rc = 0, tries = 250;
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u8 ima_opr_sts = 0;
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/*
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@ -176,17 +281,17 @@ static int fg_check_iacs_ready(struct fg_chip *chip)
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if (ima_opr_sts & IACS_RDY_BIT)
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break;
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if (!(--timeout))
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if (!(--tries))
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break;
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/* delay for iacs_ready to be asserted */
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usleep_range(5000, 7000);
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}
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if (!timeout) {
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if (!tries) {
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pr_err("IACS_RDY not set\n");
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rc = fg_check_for_ima_errors(chip);
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/* check for error condition */
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rc = fg_clear_ima_errors_if_any(chip, false);
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if (rc < 0) {
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pr_err("Failed to check for ima errors rc=%d\n", rc);
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return rc;
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@ -250,7 +355,7 @@ static int __fg_interleaved_mem_write(struct fg_chip *chip, u16 address,
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}
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/* check for error condition */
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rc = fg_check_for_ima_errors(chip);
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rc = fg_clear_ima_errors_if_any(chip, false);
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if (rc < 0) {
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pr_err("Failed to check for ima errors rc=%d\n", rc);
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return rc;
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@ -296,7 +401,7 @@ static int __fg_interleaved_mem_read(struct fg_chip *chip, u16 address,
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offset = 0;
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/* check for error condition */
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rc = fg_check_for_ima_errors(chip);
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rc = fg_clear_ima_errors_if_any(chip, false);
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if (rc < 0) {
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pr_err("Failed to check for ima errors rc=%d\n", rc);
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return rc;
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@ -581,5 +686,19 @@ int fg_ima_init(struct fg_chip *chip)
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return rc;
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}
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/* Clear DMA errors if any before clearing IMA errors */
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rc = fg_clear_dma_errors_if_any(chip);
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if (rc < 0) {
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pr_err("Error in checking DMA errors rc:%d\n", rc);
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return rc;
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}
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/* Clear IMA errors if any before SRAM transactions can begin */
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rc = fg_clear_ima_errors_if_any(chip, true);
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if (rc < 0 && rc != -EAGAIN) {
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pr_err("Error in checking IMA errors rc:%d\n", rc);
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return rc;
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}
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return 0;
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}
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@ -258,6 +258,7 @@
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#define ESR_REQ_CTL_EN_BIT BIT(0)
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/* FG_MEM_IF register and bit definitions */
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#define MEM_IF_INT_RT_STS(chip) ((chip->mem_if_base) + 0x10)
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#define MEM_IF_MEM_INTF_CFG(chip) ((chip->mem_if_base) + 0x50)
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#define MEM_IF_IMA_CTL(chip) ((chip->mem_if_base) + 0x51)
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#define MEM_IF_IMA_CFG(chip) ((chip->mem_if_base) + 0x52)
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@ -273,6 +274,11 @@
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#define MEM_IF_WR_DATA3(chip) ((chip->mem_if_base) + 0x66)
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#define MEM_IF_RD_DATA0(chip) ((chip->mem_if_base) + 0x67)
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#define MEM_IF_RD_DATA3(chip) ((chip->mem_if_base) + 0x6A)
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#define MEM_IF_DMA_STS(chip) ((chip->mem_if_base) + 0x70)
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#define MEM_IF_DMA_CTL(chip) ((chip->mem_if_base) + 0x71)
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/* MEM_IF_INT_RT_STS */
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#define MEM_XCP_BIT BIT(1)
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/* MEM_IF_MEM_INTF_CFG */
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#define MEM_ACCESS_REQ_BIT BIT(7)
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@ -286,10 +292,19 @@
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/* MEM_IF_IMA_CFG */
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#define IACS_CLR_BIT BIT(2)
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#define IACS_INTR_SRC_SLCT_BIT BIT(3)
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#define STATIC_CLK_EN_BIT BIT(4)
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/* MEM_IF_IMA_OPR_STS */
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#define IACS_RDY_BIT BIT(1)
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/* MEM_IF_IMA_EXP_STS */
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#define IACS_ERR_BIT BIT(0)
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#define XCT_TYPE_ERR_BIT BIT(1)
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#define DATA_RD_ERR_BIT BIT(3)
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#define DATA_WR_ERR_BIT BIT(4)
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#define ADDR_BURST_WRAP_BIT BIT(5)
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#define ADDR_STABLE_ERR_BIT BIT(7)
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/* MEM_IF_IMA_ERR_STS */
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#define ADDR_STBL_ERR_BIT BIT(7)
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#define WR_ACS_ERR_BIT BIT(6)
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@ -297,4 +312,11 @@
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/* MEM_IF_FG_BEAT_COUNT */
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#define BEAT_COUNT_MASK GENMASK(3, 0)
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/* MEM_IF_DMA_STS */
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#define DMA_WRITE_ERROR_BIT BIT(1)
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#define DMA_READ_ERROR_BIT BIT(2)
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/* MEM_IF_DMA_CTL */
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#define DMA_CLEAR_LOG_BIT BIT(0)
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#endif
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@ -2267,6 +2267,37 @@ static int fg_memif_init(struct fg_chip *chip)
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/* INTERRUPT HANDLERS STAY HERE */
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static irqreturn_t fg_mem_xcp_irq_handler(int irq, void *data)
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{
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struct fg_chip *chip = data;
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u8 status;
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int rc;
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rc = fg_read(chip, MEM_IF_INT_RT_STS(chip), &status, 1);
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if (rc < 0) {
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pr_err("failed to read addr=0x%04x, rc=%d\n",
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MEM_IF_INT_RT_STS(chip), rc);
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return IRQ_HANDLED;
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}
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fg_dbg(chip, FG_IRQ, "irq %d triggered, status:%d\n", irq, status);
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if (status & MEM_XCP_BIT) {
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rc = fg_clear_dma_errors_if_any(chip);
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if (rc < 0) {
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pr_err("Error in clearing DMA error, rc=%d\n", rc);
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return IRQ_HANDLED;
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}
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mutex_lock(&chip->sram_rw_lock);
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rc = fg_clear_ima_errors_if_any(chip, true);
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if (rc < 0 && rc != -EAGAIN)
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pr_err("Error in checking IMA errors rc:%d\n", rc);
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mutex_unlock(&chip->sram_rw_lock);
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}
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return IRQ_HANDLED;
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}
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static irqreturn_t fg_vbatt_low_irq_handler(int irq, void *data)
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{
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struct fg_chip *chip = data;
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@ -2483,7 +2514,7 @@ static struct fg_irq_info fg_irqs[FG_IRQ_MAX] = {
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},
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[MEM_XCP_IRQ] = {
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.name = "mem-xcp",
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.handler = fg_dummy_irq_handler,
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.handler = fg_mem_xcp_irq_handler,
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},
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[IMA_RDY_IRQ] = {
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.name = "ima-rdy",
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