Merge "msm: kgsl: Log clk set, enable and prepare failure"
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1 changed files with 85 additions and 25 deletions
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@ -81,6 +81,12 @@ static void kgsl_pwrctrl_set_state(struct kgsl_device *device,
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static void kgsl_pwrctrl_request_state(struct kgsl_device *device,
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unsigned int state);
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static int _isense_clk_set_rate(struct kgsl_pwrctrl *pwr, int level);
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static int kgsl_pwrctrl_clk_set_rate(struct clk *grp_clk, unsigned int freq,
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const char *name);
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static void _gpu_clk_prepare_enable(struct kgsl_device *device,
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struct clk *clk, const char *name);
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static void _bimc_clk_prepare_enable(struct kgsl_device *device,
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struct clk *clk, const char *name);
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/**
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* _record_pwrevent() - Record the history of the new event
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@ -405,7 +411,8 @@ void kgsl_pwrctrl_pwrlevel_change(struct kgsl_device *device,
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pwrlevel = &pwr->pwrlevels[pwr->active_pwrlevel];
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/* Change register settings if any BEFORE pwrlevel change*/
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kgsl_pwrctrl_pwrlevel_change_settings(device, 0);
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clk_set_rate(pwr->grp_clks[0], pwrlevel->gpu_freq);
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kgsl_pwrctrl_clk_set_rate(pwr->grp_clks[0],
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pwrlevel->gpu_freq, clocks[0]);
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_isense_clk_set_rate(pwr, pwr->active_pwrlevel);
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trace_kgsl_pwrlevel(device,
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@ -423,9 +430,12 @@ void kgsl_pwrctrl_pwrlevel_change(struct kgsl_device *device,
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if (pwr->gpu_bimc_int_clk) {
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if (pwr->active_pwrlevel == 0 &&
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!pwr->gpu_bimc_interface_enabled) {
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clk_set_rate(pwr->gpu_bimc_int_clk,
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pwr->gpu_bimc_int_clk_freq);
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clk_prepare_enable(pwr->gpu_bimc_int_clk);
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kgsl_pwrctrl_clk_set_rate(pwr->gpu_bimc_int_clk,
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pwr->gpu_bimc_int_clk_freq,
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"bimc_gpu_clk");
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_bimc_clk_prepare_enable(device,
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pwr->gpu_bimc_int_clk,
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"bimc_gpu_clk");
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pwr->gpu_bimc_interface_enabled = 1;
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} else if (pwr->previous_pwrlevel == 0
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&& pwr->gpu_bimc_interface_enabled) {
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@ -1650,9 +1660,9 @@ static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state,
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(requested_state != KGSL_STATE_NAP)) {
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for (i = KGSL_MAX_CLKS - 1; i > 0; i--)
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clk_unprepare(pwr->grp_clks[i]);
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clk_set_rate(pwr->grp_clks[0],
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kgsl_pwrctrl_clk_set_rate(pwr->grp_clks[0],
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pwr->pwrlevels[pwr->num_pwrlevels - 1].
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gpu_freq);
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gpu_freq, clocks[0]);
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_isense_clk_set_rate(pwr,
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pwr->num_pwrlevels - 1);
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}
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@ -1664,9 +1674,9 @@ static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state,
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for (i = KGSL_MAX_CLKS - 1; i > 0; i--)
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clk_unprepare(pwr->grp_clks[i]);
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if ((pwr->pwrlevels[0].gpu_freq > 0)) {
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clk_set_rate(pwr->grp_clks[0],
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kgsl_pwrctrl_clk_set_rate(pwr->grp_clks[0],
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pwr->pwrlevels[pwr->num_pwrlevels - 1].
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gpu_freq);
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gpu_freq, clocks[0]);
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_isense_clk_set_rate(pwr,
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pwr->num_pwrlevels - 1);
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}
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@ -1679,29 +1689,31 @@ static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state,
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/* High latency clock maintenance. */
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if (device->state != KGSL_STATE_NAP) {
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if (pwr->pwrlevels[0].gpu_freq > 0) {
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clk_set_rate(pwr->grp_clks[0],
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kgsl_pwrctrl_clk_set_rate(
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pwr->grp_clks[0],
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pwr->pwrlevels
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[pwr->active_pwrlevel].
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gpu_freq);
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gpu_freq, clocks[0]);
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_isense_clk_set_rate(pwr,
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pwr->active_pwrlevel);
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}
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for (i = KGSL_MAX_CLKS - 1; i > 0; i--)
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clk_prepare(pwr->grp_clks[i]);
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}
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/* as last step, enable grp_clk
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this is to let GPU interrupt to come */
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for (i = KGSL_MAX_CLKS - 1; i > 0; i--)
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clk_enable(pwr->grp_clks[i]);
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_gpu_clk_prepare_enable(device,
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pwr->grp_clks[i], clocks[i]);
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/* Enable the gpu-bimc-interface clocks */
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if (pwr->gpu_bimc_int_clk) {
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if (pwr->active_pwrlevel == 0 &&
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!pwr->gpu_bimc_interface_enabled) {
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clk_set_rate(pwr->gpu_bimc_int_clk,
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pwr->gpu_bimc_int_clk_freq);
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clk_prepare_enable(
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pwr->gpu_bimc_int_clk);
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kgsl_pwrctrl_clk_set_rate(
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pwr->gpu_bimc_int_clk,
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pwr->gpu_bimc_int_clk_freq,
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"bimc_gpu_clk");
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_bimc_clk_prepare_enable(device,
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pwr->gpu_bimc_int_clk,
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"bimc_gpu_clk");
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pwr->gpu_bimc_interface_enabled = 1;
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}
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}
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@ -2022,7 +2034,54 @@ static int _isense_clk_set_rate(struct kgsl_pwrctrl *pwr, int level)
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rate = clk_round_rate(pwr->grp_clks[pwr->isense_clk_indx],
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level > pwr->isense_clk_on_level ?
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KGSL_XO_CLK_FREQ : KGSL_ISENSE_CLK_FREQ);
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return clk_set_rate(pwr->grp_clks[pwr->isense_clk_indx], rate);
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return kgsl_pwrctrl_clk_set_rate(pwr->grp_clks[pwr->isense_clk_indx],
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rate, clocks[pwr->isense_clk_indx]);
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}
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/*
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* _gpu_clk_prepare_enable - Enable the specified GPU clock
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* Try once to enable it and then BUG() for debug
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*/
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static void _gpu_clk_prepare_enable(struct kgsl_device *device,
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struct clk *clk, const char *name)
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{
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int ret;
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if (device->state == KGSL_STATE_NAP) {
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ret = clk_enable(clk);
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if (ret)
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goto err;
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return;
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}
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ret = clk_prepare_enable(clk);
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if (!ret)
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return;
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err:
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/* Failure is fatal so BUG() to facilitate debug */
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KGSL_DRV_FATAL(device, "KGSL:%s enable error:%d\n", name, ret);
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}
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/*
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* _bimc_clk_prepare_enable - Enable the specified GPU clock
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* Try once to enable it and then BUG() for debug
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*/
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static void _bimc_clk_prepare_enable(struct kgsl_device *device,
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struct clk *clk, const char *name)
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{
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int ret = clk_prepare_enable(clk);
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/* Failure is fatal so BUG() to facilitate debug */
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if (ret)
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KGSL_DRV_FATAL(device, "KGSL:%s enable error:%d\n", name, ret);
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}
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static int kgsl_pwrctrl_clk_set_rate(struct clk *grp_clk, unsigned int freq,
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const char *name)
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{
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int ret = clk_set_rate(grp_clk, freq);
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WARN(ret, "KGSL:%s set freq %d failed:%d\n", name, freq, ret);
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return ret;
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}
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static inline void _close_pcl(struct kgsl_pwrctrl *pwr)
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@ -2117,11 +2176,12 @@ int kgsl_pwrctrl_init(struct kgsl_device *device)
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pwr->pwrlevels[i].gpu_freq = freq;
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}
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clk_set_rate(pwr->grp_clks[0],
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pwr->pwrlevels[pwr->num_pwrlevels - 1].gpu_freq);
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kgsl_pwrctrl_clk_set_rate(pwr->grp_clks[0],
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pwr->pwrlevels[pwr->num_pwrlevels - 1].gpu_freq, clocks[0]);
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clk_set_rate(pwr->grp_clks[6],
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clk_round_rate(pwr->grp_clks[6], KGSL_RBBMTIMER_CLK_FREQ));
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kgsl_pwrctrl_clk_set_rate(pwr->grp_clks[6],
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clk_round_rate(pwr->grp_clks[6], KGSL_RBBMTIMER_CLK_FREQ),
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clocks[6]);
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_isense_clk_set_rate(pwr, pwr->num_pwrlevels - 1);
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