From e4c1b74bb94c6760faadc34b900b5c510001f64a Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Mon, 13 Jul 2015 14:46:13 -0700 Subject: [PATCH] msm: pcie: slow down PCIe PHY RX clock for SVS mode In order for PCIe to reliabily work in SVS mode, the PCIe PHY RX clock needs to be slowed. Change-Id: Ic6edf487011ef4ac71d486210b1f6176e2142551 Signed-off-by: Tony Truong --- drivers/pci/host/pci-msm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index b2f49f60068e..0a2a4fa4869f 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -117,6 +117,7 @@ #define QSERDES_RX_N_SIGDET_ENABLES(n, m) (RX(n, m) + 0x110) #define QSERDES_RX_N_SIGDET_DEGLITCH_CNTRL(n, m) (RX(n, m) + 0x11C) #define QSERDES_RX_N_SIGDET_LVL(n, m) (RX(n, m) + 0x118) +#define QSERDES_RX_N_RX_BAND(n, m) (RX(n, m) + 0x120) #define PCIE_N_SW_RESET(n, m) (PCS_PORT(n, m) + 0x00) #define PCIE_N_POWER_DOWN_CONTROL(n, m) (PCS_PORT(n, m) + 0x04) @@ -1178,6 +1179,9 @@ static void pcie_pcs_port_phy_init(struct msm_pcie_dev_t *dev) msm_pcie_write_reg(dev->phy, QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL4(dev->rc_idx, common_phy), 0xDB); + msm_pcie_write_reg(dev->phy, + QSERDES_RX_N_RX_BAND(dev->rc_idx, common_phy), + 0x18); msm_pcie_write_reg(dev->phy, QSERDES_RX_N_UCDR_SO_GAIN(dev->rc_idx, common_phy), 0x04);