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[ARM] 5310/1: Fix cache flush functions for ARMv4

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ARMv4 (ARM720T) cache flush functions are broken in 2.6.19+ kernels.
The issue was introduced by commit f12d0d7c77
This patch corrects the CPU_CP15 ifdef statements so that they actually
do something.

Signed-off-by: Anders Grafström <grfstrm@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Anders Grafström 2008-10-16 17:37:24 +01:00 • committed by Russell King
parent 957cf333b5
commit e4d2a5985a
1 changed files with 3 additions and 3 deletions
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6
arch/arm/mm/cache-v4.S
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@ -29,7 +29,7 @@ ENTRY(v4_flush_user_cache_all)
* Clean and invalidate the entire cache. * Clean and invalidate the entire cache.
*/ */
ENTRY(v4_flush_kern_cache_all) ENTRY(v4_flush_kern_cache_all)
#ifdef CPU_CP15 #ifdef CONFIG_CPU_CP15
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ flush ID cache mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
mov pc, lr mov pc, lr
@ -48,7 +48,7 @@ ENTRY(v4_flush_kern_cache_all)
* - flags - vma_area_struct flags describing address space * - flags - vma_area_struct flags describing address space
*/ */
ENTRY(v4_flush_user_cache_range) ENTRY(v4_flush_user_cache_range)
#ifdef CPU_CP15 #ifdef CONFIG_CPU_CP15
mov ip, #0 mov ip, #0
mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache mcreq p15, 0, ip, c7, c7, 0 @ flush ID cache
mov pc, lr mov pc, lr
@ -116,7 +116,7 @@ ENTRY(v4_dma_inv_range)
* - end - virtual end address * - end - virtual end address
*/ */
ENTRY(v4_dma_flush_range) ENTRY(v4_dma_flush_range)
#ifdef CPU_CP15 #ifdef CONFIG_CPU_CP15
mov r0, #0 mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ flush ID cache mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
#endif #endif