From 80f8b9c75301d12a40912f3ebab4504e0e846d35 Mon Sep 17 00:00:00 2001
From: Shankar Ravi <rshankar@codeaurora.org>
Date: Fri, 24 Mar 2017 17:03:55 +0530
Subject: [PATCH] ARM: dts: msm: Update camera clock sources for sdm630

Changing the clock source frequencies to lower
working frequencies so that the camera runs in
SVS_L1 mode, which reduces the power consumption.

Change-Id: I47c105dafa96879c5607acae4680f3b189f4941a
Signed-off-by: Shankar Ravi <rshankar@codeaurora.org>
---
 arch/arm/boot/dts/qcom/sdm630-camera.dtsi | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/boot/dts/qcom/sdm630-camera.dtsi b/arch/arm/boot/dts/qcom/sdm630-camera.dtsi
index 82b9b2cf4de8..5923689c071e 100644
--- a/arch/arm/boot/dts/qcom/sdm630-camera.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm630-camera.dtsi
@@ -54,8 +54,8 @@
 			"csiphy_timer_src_clk", "csiphy_timer_clk",
 			"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk",
 			"csiphy_ahb2crif";
-		qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0
-			0 384000000 0 0>;
+		qcom,clock-rates = <0 0 0 0 0 0 310000000 0 0 269333333 0
+			0 200000000 0 0>;
 		status = "ok";
 	};
 
@@ -92,8 +92,8 @@
 			"csiphy_timer_src_clk", "csiphy_timer_clk",
 			"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk",
 			"csiphy_ahb2crif";
-		qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0
-			0 384000000 0 0>;
+		qcom,clock-rates = <0 0 0 0 0 0 310000000 0 0 269333333 0
+			0 200000000 0 0>;
 		status = "ok";
 	};
 
@@ -130,8 +130,8 @@
 			"csiphy_timer_src_clk", "csiphy_timer_clk",
 			"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk",
 			"csiphy_ahb2crif";
-		qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0
-			0 384000000 0 0>;
+		qcom,clock-rates = <0 0 0 0 0 0 310000000 0 0 269333333 0
+			0 200000000 0 0>;
 		status = "ok";
 	};
 
@@ -171,7 +171,7 @@
 			"ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
 			"csi_clk", "csi_ahb_clk", "csi_rdi_clk",
 			"csi_pix_clk", "cphy_csid_clk";
-		qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000
+		qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
 			0 0 0 0 0>;
 		status = "ok";
 	};
@@ -212,7 +212,7 @@
 			"ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
 			"csi_clk", "csi_ahb_clk", "csi_rdi_clk",
 			"csi_pix_clk", "cphy_csid_clk";
-		qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000
+		qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
 			 0 0 0 0 0>;
 		status = "ok";
 	};
@@ -253,7 +253,7 @@
 			"ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
 			"csi_clk", "csi_ahb_clk", "csi_rdi_clk",
 			"csi_pix_clk", "cphy_csid_clk";
-		qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000
+		qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
 			 0 0 0 0 0>;
 		status = "ok";
 	};
@@ -294,7 +294,7 @@
 			"ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
 			"csi_clk", "csi_ahb_clk", "csi_rdi_clk",
 			"csi_pix_clk", "cphy_csid_clk";
-		qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000
+		qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
 			 0 0 0 0 0>;
 		status = "ok";
 	};