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ARM: dts: msm: Add camera sensor module nodes for msmcobalt

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Add CCI, CSIPHY, CSID, camera, actuator, eeprom, ois
dtsi entries for msmcobalt.

Change-Id: I933ae498a243cc6d5a38e8553043b30425683ffe
Signed-off-by: Sureshnaidu Laveti <lsuresh@codeaurora.org>
This commit is contained in:
Sureshnaidu Laveti 2016-04-07 01:53:20 -07:00 • committed by Bryan Huntsman
parent 3599fad412
commit ea024084d7
10 changed files with 1525 additions and 10 deletions
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301
arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-cdp.dtsi Normal file
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@ -0,0 +1,301 @@
/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&cci {
actuator0: qcom,actuator@0 {
cell-index = <0>;
reg = <0x0>;
compatible = "qcom,actuator";
qcom,cci-master = <0>;
gpios = <&tlmm 27 0>;
qcom,gpio-vaf = <0>;
qcom,gpio-req-tbl-num = <0>;
qcom,gpio-req-tbl-flags = <0>;
qcom,gpio-req-tbl-label = "CAM_VAF";
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_actuator_vaf_active
&cam_actuator_vaf_suspend>;
pinctrl-1 = <&cam_actuator_vaf_active
&cam_actuator_vaf_suspend>;
};
actuator1: qcom,actuator@1 {
cell-index = <1>;
reg = <0x1>;
compatible = "qcom,actuator";
qcom,cci-master = <1>;
gpios = <&tlmm 27 0>;
qcom,gpio-vaf = <0>;
qcom,gpio-req-tbl-num = <0>;
qcom,gpio-req-tbl-flags = <0>;
qcom,gpio-req-tbl-label = "CAM_VAF";
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_actuator_vaf_active
&cam_actuator_vaf_suspend>;
pinctrl-1 = <&cam_actuator_vaf_active
&cam_actuator_vaf_suspend>;
};
ois0: qcom,ois@0 {
cell-index = <0>;
reg = <0x0>;
compatible = "qcom,ois";
qcom,cci-master = <0>;
gpios = <&tlmm 27 0>;
qcom,gpio-vaf = <0>;
qcom,gpio-req-tbl-num = <0>;
qcom,gpio-req-tbl-flags = <0>;
qcom,gpio-req-tbl-label = "CAM_VAF";
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_actuator_vaf_active
&cam_actuator_vaf_suspend>;
pinctrl-1 = <&cam_actuator_vaf_active
&cam_actuator_vaf_suspend>;
};
eeprom0: qcom,eeprom@0 {
cell-index = <0>;
reg = <0>;
compatible = "qcom,eeprom";
cam_vio-supply = <&pmcobalt_lvs1>;
cam_vana-supply = <&pmicobalt_bob>;
cam_vdig-supply = <&pmcobalt_s3>;
qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
qcom,cam-vreg-min-voltage = <0 3312000 1352000>;
qcom,cam-vreg-max-voltage = <0 3312000 1352000>;
qcom,cam-vreg-op-mode = <0 80000 105000>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk0_active
&cam_sensor_rear_active>;
pinctrl-1 = <&cam_sensor_mclk0_suspend
&cam_sensor_rear_suspend>;
gpios = <&tlmm 13 0>,
<&tlmm 30 0>,
<&pmcobalt_gpios 20 0>,
<&tlmm 29 0>;
qcom,gpio-reset = <1>;
qcom,gpio-vdig = <2>;
qcom,gpio-vana = <3>;
qcom,gpio-req-tbl-num = <0 1 2 3>;
qcom,gpio-req-tbl-flags = <1 0 0 0>;
qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0",
"CAM_VDIG",
"CAM_VANA";
qcom,sensor-position = <0>;
qcom,sensor-mode = <0>;
qcom,cci-master = <0>;
status = "ok";
clocks = <&clock_mmss clk_mclk0_clk_src>,
<&clock_mmss clk_mmss_camss_mclk0_clk>;
clock-names = "cam_src_clk", "cam_clk";
qcom,clock-rates = <24000000 0>;
};
eeprom1: qcom,eeprom@1 {
cell-index = <1>;
reg = <0x1>;
compatible = "qcom,eeprom";
cam_vio-supply = <&pmcobalt_lvs1>;
cam_vana-supply = <&pmcobalt_l22>;
cam_vdig-supply = <&pmcobalt_s3>;
qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
qcom,cam-vreg-min-voltage =
<0 2864000 1352000>;
qcom,cam-vreg-max-voltage =
<0 2864000 1352000>;
qcom,cam-vreg-op-mode = <0 80000 105000>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk2_active
&cam_sensor_front_active>;
pinctrl-1 = <&cam_sensor_mclk2_suspend
&cam_sensor_front_suspend>;
gpios = <&tlmm 14 0>,
<&tlmm 28 0>,
<&tlmm 27 0>,
<&pmcobalt_gpios 9 0>;
qcom,gpio-reset = <1>;
qcom,gpio-standby = <2>;
qcom,gpio-vdig = <3>;
qcom,gpio-req-tbl-num = <0 1 2 3>;
qcom,gpio-req-tbl-flags = <1 0 0 0>;
qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2",
"CAM_STANDBY2",
"CAM_VDIG";
qcom,sensor-position = <1>;
qcom,sensor-mode = <0>;
qcom,cci-master = <1>;
status = "ok";
clocks = <&clock_mmss clk_mclk2_clk_src>,
<&clock_mmss clk_mmss_camss_mclk2_clk>;
clock-names = "cam_src_clk", "cam_clk";
qcom,clock-rates = <24000000 0>;
};
qcom,camera@0 {
cell-index = <0>;
compatible = "qcom,camera";
reg = <0x0>;
qcom,csiphy-sd-index = <0>;
qcom,csid-sd-index = <0>;
qcom,mount-angle = <90>;
qcom,actuator-src = <&actuator0>;
qcom,ois-src = <&ois0>;
qcom,eeprom-src = <&eeprom0>;
cam_vio-supply = <&pmcobalt_lvs1>;
cam_vana-supply = <&pmicobalt_bob>;
cam_vdig-supply = <&pmcobalt_s3>;
qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
qcom,cam-vreg-min-voltage = <0 3312000 1352000>;
qcom,cam-vreg-max-voltage = <0 3312000 1352000>;
qcom,cam-vreg-op-mode = <0 80000 105000>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk0_active
&cam_sensor_rear_active>;
pinctrl-1 = <&cam_sensor_mclk0_suspend
&cam_sensor_rear_suspend>;
gpios = <&tlmm 13 0>,
<&tlmm 30 0>,
<&pmcobalt_gpios 20 0>,
<&tlmm 29 0>;
qcom,gpio-reset = <1>;
qcom,gpio-vdig = <2>;
qcom,gpio-vana = <3>;
qcom,gpio-req-tbl-num = <0 1 2 3>;
qcom,gpio-req-tbl-flags = <1 0 0 0>;
qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0",
"CAM_VDIG",
"CAM_VANA";
qcom,sensor-position = <0>;
qcom,sensor-mode = <0>;
qcom,cci-master = <0>;
status = "ok";
clocks = <&clock_mmss clk_mclk0_clk_src>,
<&clock_mmss clk_mmss_camss_mclk0_clk>;
clock-names = "cam_src_clk", "cam_clk";
qcom,clock-rates = <24000000 0>;
};
qcom,camera@1 {
cell-index = <1>;
compatible = "qcom,camera";
reg = <0x1>;
qcom,csiphy-sd-index = <1>;
qcom,csid-sd-index = <1>;
qcom,mount-angle = <90>;
cam_vdig-supply = <&pmcobalt_lvs1>;
cam_vio-supply = <&pmcobalt_lvs1>;
cam_vana-supply = <&pmicobalt_bob>;
qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana";
qcom,cam-vreg-min-voltage = <0 0 3312000>;
qcom,cam-vreg-max-voltage = <0 0 3312000>;
qcom,cam-vreg-op-mode = <0 0 80000>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk1_active
&cam_sensor_rear2_active>;
pinctrl-1 = <&cam_sensor_mclk1_suspend
&cam_sensor_rear2_suspend>;
gpios = <&tlmm 15 0>,
<&tlmm 9 0>,
<&tlmm 8 0>;
qcom,gpio-reset = <1>;
qcom,gpio-vana = <2>;
qcom,gpio-req-tbl-num = <0 1 2>;
qcom,gpio-req-tbl-flags = <1 0 0>;
qcom,gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1",
"CAM_VANA1";
qcom,sensor-position = <0>;
qcom,sensor-mode = <0>;
qcom,cci-master = <0>;
status = "ok";
clocks = <&clock_mmss clk_mclk1_clk_src>,
<&clock_mmss clk_mmss_camss_mclk1_clk>;
clock-names = "cam_src_clk", "cam_clk";
qcom,clock-rates = <24000000 0>;
};
qcom,camera@2 {
cell-index = <2>;
compatible = "qcom,camera";
reg = <0x02>;
qcom,csiphy-sd-index = <2>;
qcom,csid-sd-index = <2>;
qcom,mount-angle = <90>;
qcom,eeprom-src = <&eeprom1>;
qcom,actuator-src = <&actuator1>;
cam_vio-supply = <&pmcobalt_lvs1>;
cam_vana-supply = <&pmcobalt_l22>;
cam_vdig-supply = <&pmcobalt_s3>;
qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
qcom,cam-vreg-min-voltage =
<0 2864000 1352000>;
qcom,cam-vreg-max-voltage =
<0 2864000 1352000>;
qcom,cam-vreg-op-mode = <0 80000 105000>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk2_active
&cam_sensor_front_active>;
pinctrl-1 = <&cam_sensor_mclk2_suspend
&cam_sensor_front_suspend>;
gpios = <&tlmm 14 0>,
<&tlmm 28 0>,
<&tlmm 27 0>,
<&pmcobalt_gpios 9 0>;
qcom,gpio-reset = <1>;
qcom,gpio-standby = <2>;
qcom,gpio-vdig = <3>;
qcom,gpio-req-tbl-num = <0 1 2 3>;
qcom,gpio-req-tbl-flags = <1 0 0 0>;
qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2",
"CAM_STANDBY2",
"CAM_VDIG";
qcom,sensor-position = <1>;
qcom,sensor-mode = <0>;
qcom,cci-master = <1>;
status = "ok";
clocks = <&clock_mmss clk_mclk2_clk_src>,
<&clock_mmss clk_mmss_camss_mclk2_clk>;
clock-names = "cam_src_clk", "cam_clk";
qcom,clock-rates = <24000000 0>;
};
};
&pmcobalt_gpios {
gpio@c800 { /* GPIO 9 - CAMERA SENSOR 2 VDIG */
qcom,mode = <1>; /* Output*/
qcom,pull = <4>; /* Pulldown 10uA */
qcom,vin-sel = <1>; /* VIN1 GPIO_MV */
qcom,src-sel = <0>; /* GPIO */
qcom,invert = <0>; /* Invert */
qcom,master-en = <1>; /* Enable GPIO */
status = "ok";
};
gpio@d300 { /* GPIO 20 - CAMERA SENSOR 0 VDIG */
qcom,mode = <1>; /* Output*/
qcom,pull = <4>; /* Pulldown 10uA */
qcom,vin-sel = <1>; /* VIN1 GPIO_MV*/
qcom,src-sel = <0>; /* GPIO */
qcom,invert = <0>; /* Invert */
qcom,master-en = <1>; /* Enable GPIO */
status = "ok";
};
};

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arch/arm/boot/dts/qcom/msmcobalt-camera-sensor-mtp.dtsi Normal file
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/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&cci {
actuator0: qcom,actuator@0 {
cell-index = <0>;
reg = <0x0>;
compatible = "qcom,actuator";
qcom,cci-master = <0>;
gpios = <&tlmm 27 0>;
qcom,gpio-vaf = <0>;
qcom,gpio-req-tbl-num = <0>;
qcom,gpio-req-tbl-flags = <0>;
qcom,gpio-req-tbl-label = "CAM_VAF";
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_actuator_vaf_active
&cam_actuator_vaf_suspend>;
pinctrl-1 = <&cam_actuator_vaf_active
&cam_actuator_vaf_suspend>;
};
actuator1: qcom,actuator@1 {
cell-index = <1>;
reg = <0x1>;
compatible = "qcom,actuator";
qcom,cci-master = <1>;
gpios = <&tlmm 27 0>;
qcom,gpio-vaf = <0>;
qcom,gpio-req-tbl-num = <0>;
qcom,gpio-req-tbl-flags = <0>;
qcom,gpio-req-tbl-label = "CAM_VAF";
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_actuator_vaf_active
&cam_actuator_vaf_suspend>;
pinctrl-1 = <&cam_actuator_vaf_active
&cam_actuator_vaf_suspend>;
};
ois0: qcom,ois@0 {
cell-index = <0>;
reg = <0x0>;
compatible = "qcom,ois";
qcom,cci-master = <0>;
gpios = <&tlmm 27 0>;
qcom,gpio-vaf = <0>;
qcom,gpio-req-tbl-num = <0>;
qcom,gpio-req-tbl-flags = <0>;
qcom,gpio-req-tbl-label = "CAM_VAF";
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_actuator_vaf_active
&cam_actuator_vaf_suspend>;
pinctrl-1 = <&cam_actuator_vaf_active
&cam_actuator_vaf_suspend>;
};
eeprom0: qcom,eeprom@0 {
cell-index = <0>;
reg = <0>;
compatible = "qcom,eeprom";
cam_vio-supply = <&pmcobalt_lvs1>;
cam_vana-supply = <&pmicobalt_bob>;
cam_vdig-supply = <&pmcobalt_s3>;
qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
qcom,cam-vreg-min-voltage = <0 3312000 1352000>;
qcom,cam-vreg-max-voltage = <0 3312000 1352000>;
qcom,cam-vreg-op-mode = <0 80000 105000>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk0_active
&cam_sensor_rear_active>;
pinctrl-1 = <&cam_sensor_mclk0_suspend
&cam_sensor_rear_suspend>;
gpios = <&tlmm 13 0>,
<&tlmm 30 0>,
<&pmcobalt_gpios 20 0>,
<&tlmm 29 0>;
qcom,gpio-reset = <1>;
qcom,gpio-vdig = <2>;
qcom,gpio-vana = <3>;
qcom,gpio-req-tbl-num = <0 1 2 3>;
qcom,gpio-req-tbl-flags = <1 0 0 0>;
qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0",
"CAM_VDIG",
"CAM_VANA";
qcom,sensor-position = <0>;
qcom,sensor-mode = <0>;
qcom,cci-master = <0>;
status = "ok";
clocks = <&clock_mmss clk_mclk0_clk_src>,
<&clock_mmss clk_mmss_camss_mclk0_clk>;
clock-names = "cam_src_clk", "cam_clk";
qcom,clock-rates = <24000000 0>;
};
eeprom1: qcom,eeprom@1 {
cell-index = <1>;
reg = <0x1>;
compatible = "qcom,eeprom";
cam_vio-supply = <&pmcobalt_lvs1>;
cam_vana-supply = <&pmcobalt_l22>;
cam_vdig-supply = <&pmcobalt_s3>;
qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
qcom,cam-vreg-min-voltage =
<0 2864000 1352000>;
qcom,cam-vreg-max-voltage =
<0 2864000 1352000>;
qcom,cam-vreg-op-mode = <0 80000 105000>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk2_active
&cam_sensor_front_active>;
pinctrl-1 = <&cam_sensor_mclk2_suspend
&cam_sensor_front_suspend>;
gpios = <&tlmm 14 0>,
<&tlmm 28 0>,
<&tlmm 27 0>,
<&pmcobalt_gpios 9 0>;
qcom,gpio-reset = <1>;
qcom,gpio-standby = <2>;
qcom,gpio-vdig = <3>;
qcom,gpio-req-tbl-num = <0 1 2 3>;
qcom,gpio-req-tbl-flags = <1 0 0 0>;
qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2",
"CAM_STANDBY2",
"CAM_VDIG";
qcom,sensor-position = <1>;
qcom,sensor-mode = <0>;
qcom,cci-master = <1>;
status = "ok";
clocks = <&clock_mmss clk_mclk2_clk_src>,
<&clock_mmss clk_mmss_camss_mclk2_clk>;
clock-names = "cam_src_clk", "cam_clk";
qcom,clock-rates = <24000000 0>;
};
qcom,camera@0 {
cell-index = <0>;
compatible = "qcom,camera";
reg = <0x0>;
qcom,csiphy-sd-index = <0>;
qcom,csid-sd-index = <0>;
qcom,mount-angle = <90>;
qcom,actuator-src = <&actuator0>;
qcom,ois-src = <&ois0>;
qcom,eeprom-src = <&eeprom0>;
cam_vio-supply = <&pmcobalt_lvs1>;
cam_vana-supply = <&pmicobalt_bob>;
cam_vdig-supply = <&pmcobalt_s3>;
qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
qcom,cam-vreg-min-voltage = <0 3312000 1352000>;
qcom,cam-vreg-max-voltage = <0 3312000 1352000>;
qcom,cam-vreg-op-mode = <0 80000 105000>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk0_active
&cam_sensor_rear_active>;
pinctrl-1 = <&cam_sensor_mclk0_suspend
&cam_sensor_rear_suspend>;
gpios = <&tlmm 13 0>,
<&tlmm 30 0>,
<&pmcobalt_gpios 20 0>,
<&tlmm 29 0>;
qcom,gpio-reset = <1>;
qcom,gpio-vdig = <2>;
qcom,gpio-vana = <3>;
qcom,gpio-req-tbl-num = <0 1 2 3>;
qcom,gpio-req-tbl-flags = <1 0 0 0>;
qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
"CAM_RESET0",
"CAM_VDIG",
"CAM_VANA";
qcom,sensor-position = <0>;
qcom,sensor-mode = <0>;
qcom,cci-master = <0>;
status = "ok";
clocks = <&clock_mmss clk_mclk0_clk_src>,
<&clock_mmss clk_mmss_camss_mclk0_clk>;
clock-names = "cam_src_clk", "cam_clk";
qcom,clock-rates = <24000000 0>;
};
qcom,camera@1 {
cell-index = <1>;
compatible = "qcom,camera";
reg = <0x1>;
qcom,csiphy-sd-index = <1>;
qcom,csid-sd-index = <1>;
qcom,mount-angle = <90>;
cam_vdig-supply = <&pmcobalt_lvs1>;
cam_vio-supply = <&pmcobalt_lvs1>;
cam_vana-supply = <&pmicobalt_bob>;
qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana";
qcom,cam-vreg-min-voltage = <0 0 3312000>;
qcom,cam-vreg-max-voltage = <0 0 3312000>;
qcom,cam-vreg-op-mode = <0 0 80000>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk1_active
&cam_sensor_rear2_active>;
pinctrl-1 = <&cam_sensor_mclk1_suspend
&cam_sensor_rear2_suspend>;
gpios = <&tlmm 15 0>,
<&tlmm 9 0>,
<&tlmm 8 0>;
qcom,gpio-reset = <1>;
qcom,gpio-vana = <2>;
qcom,gpio-req-tbl-num = <0 1 2>;
qcom,gpio-req-tbl-flags = <1 0 0>;
qcom,gpio-req-tbl-label = "CAMIF_MCLK1",
"CAM_RESET1",
"CAM_VANA1";
qcom,sensor-position = <0>;
qcom,sensor-mode = <0>;
qcom,cci-master = <0>;
status = "ok";
clocks = <&clock_mmss clk_mclk1_clk_src>,
<&clock_mmss clk_mmss_camss_mclk1_clk>;
clock-names = "cam_src_clk", "cam_clk";
qcom,clock-rates = <24000000 0>;
};
qcom,camera@2 {
cell-index = <2>;
compatible = "qcom,camera";
reg = <0x02>;
qcom,csiphy-sd-index = <2>;
qcom,csid-sd-index = <2>;
qcom,mount-angle = <90>;
qcom,eeprom-src = <&eeprom1>;
qcom,actuator-src = <&actuator1>;
cam_vio-supply = <&pmcobalt_lvs1>;
cam_vana-supply = <&pmcobalt_l22>;
cam_vdig-supply = <&pmcobalt_s3>;
qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
qcom,cam-vreg-min-voltage =
<0 2864000 1352000>;
qcom,cam-vreg-max-voltage =
<0 2864000 1352000>;
qcom,cam-vreg-op-mode = <0 80000 105000>;
qcom,gpio-no-mux = <0>;
pinctrl-names = "cam_default", "cam_suspend";
pinctrl-0 = <&cam_sensor_mclk2_active
&cam_sensor_front_active>;
pinctrl-1 = <&cam_sensor_mclk2_suspend
&cam_sensor_front_suspend>;
gpios = <&tlmm 14 0>,
<&tlmm 28 0>,
<&tlmm 27 0>,
<&pmcobalt_gpios 9 0>;
qcom,gpio-reset = <1>;
qcom,gpio-standby = <2>;
qcom,gpio-vdig = <3>;
qcom,gpio-req-tbl-num = <0 1 2 3>;
qcom,gpio-req-tbl-flags = <1 0 0 0>;
qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
"CAM_RESET2",
"CAM_STANDBY2",
"CAM_VDIG";
qcom,sensor-position = <1>;
qcom,sensor-mode = <0>;
qcom,cci-master = <1>;
status = "ok";
clocks = <&clock_mmss clk_mclk2_clk_src>,
<&clock_mmss clk_mmss_camss_mclk2_clk>;
clock-names = "cam_src_clk", "cam_clk";
qcom,clock-rates = <24000000 0>;
};
};
&pmcobalt_gpios {
gpio@c800 { /* GPIO 9 - CAMERA SENSOR 2 VDIG */
qcom,mode = <1>; /* Output*/
qcom,pull = <4>; /* Pulldown 10uA */
qcom,vin-sel = <1>; /* VIN1 GPIO_MV */
qcom,src-sel = <0>; /* GPIO */
qcom,invert = <0>; /* Invert */
qcom,master-en = <1>; /* Enable GPIO */
status = "ok";
};
gpio@d300 { /* GPIO 20 - CAMERA SENSOR 0 VDIG */
qcom,mode = <1>; /* Output*/
qcom,pull = <4>; /* Pulldown 10uA */
qcom,vin-sel = <1>; /* VIN1 GPIO_MV*/
qcom,src-sel = <0>; /* GPIO */
qcom,invert = <0>; /* Invert */
qcom,master-en = <1>; /* Enable GPIO */
status = "ok";
};
};

284
arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi
View file

@ -21,6 +21,180 @@
qcom,bus-votes = <0 300000000 640000000 640000000>; qcom,bus-votes = <0 300000000 640000000 640000000>;
}; };
qcom,csiphy@ca34000 {
cell-index = <0>;
compatible = "qcom,csiphy-v5.0", "qcom,csiphy";
reg = <0xca34000 0x1000>;
reg-names = "csiphy";
interrupts = <0 78 0>;
interrupt-names = "csiphy";
clocks = <&clock_mmss clk_mmss_camss_top_ahb_clk>,
<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
<&clock_mmss clk_csi0phytimer_clk_src>,
<&clock_mmss clk_mmss_camss_csi0phytimer_clk>,
<&clock_mmss clk_mmss_camss_ahb_clk>,
<&clock_mmss clk_csi0_clk_src>,
<&clock_mmss clk_mmss_camss_csi0_clk>,
<&clock_mmss clk_mmss_camss_cphy_csid0_clk>;
clock-names = "camss_top_ahb_clk",
"camss_ispif_ahb_clk", "csiphy_timer_src_clk",
"csiphy_timer_clk", "camss_ahb_clk",
"csi_src_clk", "csi_clk", "cphy_csid_clk";
qcom,clock-rates = <0 0 269333333 0 0 256000000 0 0>;
};
qcom,csiphy@ca35000 {
cell-index = <1>;
compatible = "qcom,csiphy-v5.0", "qcom,csiphy";
reg = <0xca35000 0x1000>;
reg-names = "csiphy";
interrupts = <0 79 0>;
interrupt-names = "csiphy";
clocks = <&clock_mmss clk_mmss_camss_top_ahb_clk>,
<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
<&clock_mmss clk_csi1phytimer_clk_src>,
<&clock_mmss clk_mmss_camss_csi1phytimer_clk>,
<&clock_mmss clk_mmss_camss_ahb_clk>,
<&clock_mmss clk_csi1_clk_src>,
<&clock_mmss clk_mmss_camss_csi1_clk>,
<&clock_mmss clk_mmss_camss_cphy_csid1_clk>;
clock-names = "camss_top_ahb_clk",
"camss_ispif_ahb_clk", "csiphy_timer_src_clk",
"csiphy_timer_clk", "camss_ahb_clk",
"csi_src_clk", "csi_clk", "cphy_csid_clk";
qcom,clock-rates = <0 0 269333333 0 0 256000000 0 0>;
};
qcom,csiphy@ca36000 {
cell-index = <2>;
compatible = "qcom,csiphy-v5.0", "qcom,csiphy";
reg = <0xca36000 0x1000>;
reg-names = "csiphy";
interrupts = <0 80 0>;
interrupt-names = "csiphy";
clocks = <&clock_mmss clk_mmss_camss_top_ahb_clk>,
<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
<&clock_mmss clk_csi2phytimer_clk_src>,
<&clock_mmss clk_mmss_camss_csi2phytimer_clk>,
<&clock_mmss clk_mmss_camss_ahb_clk>,
<&clock_mmss clk_csi2_clk_src>,
<&clock_mmss clk_mmss_camss_csi2_clk>,
<&clock_mmss clk_mmss_camss_cphy_csid2_clk>;
clock-names = "camss_top_ahb_clk",
"camss_ispif_ahb_clk", "csiphy_timer_src_clk",
"csiphy_timer_clk", "camss_ahb_clk",
"csi_src_clk", "csi_clk", "cphy_csid_clk";
qcom,clock-rates = <0 0 269333333 0 0 256000000 0 0>;
};
qcom,csid@ca30000 {
cell-index = <0>;
compatible = "qcom,csid-v5.0", "qcom,csid";
reg = <0xca30000 0x400>;
reg-names = "csid";
interrupts = <0 296 0>;
interrupt-names = "csid";
qcom,csi-vdd-voltage = <752000>;
qcom,mipi-csi-vdd-supply = <&pmcobalt_s1_level>;
gdscr-supply = <&gdsc_camss_top>;
qcom,cam-vreg-name = "gdscr";
clocks = <&clock_mmss clk_mmss_camss_top_ahb_clk>,
<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
<&clock_mmss clk_csi0_clk_src>,
<&clock_mmss clk_mmss_camss_csi0_clk>,
<&clock_mmss clk_mmss_camss_csiphy0_clk>,
<&clock_mmss clk_mmss_camss_csi0_ahb_clk>,
<&clock_mmss clk_mmss_camss_csi0rdi_clk>,
<&clock_mmss clk_mmss_camss_csi0pix_clk>,
<&clock_mmss clk_mmss_camss_ahb_clk>;
clock-names = "camss_top_ahb_clk",
"ispif_ahb_clk", "csi_src_clk", "csi_clk",
"csi_phy_clk", "csi_ahb_clk", "csi_rdi_clk",
"csi_pix_clk", "camss_ahb_clk";
qcom,clock-rates = <0 0 256000000 0 0 0 0 0 0>;
status = "ok";
};
qcom,csid@ca30400 {
cell-index = <1>;
compatible = "qcom,csid-v5.0", "qcom,csid";
reg = <0xca30400 0x400>;
reg-names = "csid";
interrupts = <0 297 0>;
interrupt-names = "csid";
qcom,csi-vdd-voltage = <1200000>;
qcom,mipi-csi-vdd-supply = <&pmcobalt_s1_level>;
gdscr-supply = <&gdsc_camss_top>;
qcom,cam-vreg-name = "gdscr";
clocks = <&clock_mmss clk_mmss_camss_top_ahb_clk>,
<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
<&clock_mmss clk_csi1_clk_src>,
<&clock_mmss clk_mmss_camss_csi1_clk>,
<&clock_mmss clk_mmss_camss_csiphy1_clk>,
<&clock_mmss clk_mmss_camss_csi1_ahb_clk>,
<&clock_mmss clk_mmss_camss_csi1rdi_clk>,
<&clock_mmss clk_mmss_camss_csi1pix_clk>,
<&clock_mmss clk_mmss_camss_ahb_clk>;
clock-names = "camss_top_ahb_clk",
"ispif_ahb_clk", "csi_src_clk", "csi_clk",
"csi_phy_clk", "csi_ahb_clk", "csi_rdi_clk",
"csi_pix_clk", "camss_ahb_clk";
qcom,clock-rates = <0 0 256000000 0 0 0 0 0 0>;
};
qcom,csid@ca30800 {
cell-index = <2>;
compatible = "qcom,csid-v5.0", "qcom,csid";
reg = <0xca30800 0x400>;
reg-names = "csid";
interrupts = <0 298 0>;
interrupt-names = "csid";
qcom,csi-vdd-voltage = <1200000>;
qcom,mipi-csi-vdd-supply = <&pmcobalt_s1_level>;
gdscr-supply = <&gdsc_camss_top>;
qcom,cam-vreg-name = "gdscr";
clocks = <&clock_mmss clk_mmss_camss_top_ahb_clk>,
<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
<&clock_mmss clk_csi2_clk_src>,
<&clock_mmss clk_mmss_camss_csi2_clk>,
<&clock_mmss clk_mmss_camss_csiphy2_clk>,
<&clock_mmss clk_mmss_camss_csi2_ahb_clk>,
<&clock_mmss clk_mmss_camss_csi2rdi_clk>,
<&clock_mmss clk_mmss_camss_csi2pix_clk>,
<&clock_mmss clk_mmss_camss_ahb_clk>;
clock-names = "camss_top_ahb_clk",
"ispif_ahb_clk", "csi_src_clk", "csi_clk",
"csi_phy_clk", "csi_ahb_clk", "csi_rdi_clk",
"csi_pix_clk", "camss_ahb_clk";
qcom,clock-rates = <0 0 256000000 0 0 0 0 0 0>;
};
qcom,csid@ca30c00 {
cell-index = <3>;
compatible = "qcom,csid-v5.0", "qcom,csid";
reg = <0xca30c00 0x400>;
reg-names = "csid";
interrupts = <0 299 0>;
interrupt-names = "csid";
qcom,csi-vdd-voltage = <1200000>;
qcom,mipi-csi-vdd-supply = <&pmcobalt_s1_level>;
gdscr-supply = <&gdsc_camss_top>;
qcom,cam-vreg-name = "gdscr";
clocks = <&clock_mmss clk_mmss_camss_top_ahb_clk>,
<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
<&clock_mmss clk_csi0_clk_src>,
<&clock_mmss clk_mmss_camss_csi0_clk>,
<&clock_mmss clk_mmss_camss_csiphy0_clk>,
<&clock_mmss clk_mmss_camss_csi0_ahb_clk>,
<&clock_mmss clk_mmss_camss_csi0rdi_clk>,
<&clock_mmss clk_mmss_camss_csi0pix_clk>,
<&clock_mmss clk_mmss_camss_ahb_clk>;
clock-names = "camss_top_ahb_clk",
"ispif_ahb_clk", "csi_src_clk", "csi_clk",
"csi_phy_clk", "csi_ahb_clk", "csi_rdi_clk",
"csi_pix_clk", "camss_ahb_clk";
qcom,clock-rates = <0 0 256000000 0 0 0 0 0 0>;
};
qcom,cam_smmu { qcom,cam_smmu {
compatible = "qcom,msm-cam-smmu"; compatible = "qcom,msm-cam-smmu";
status = "disabled"; status = "disabled";
@ -396,4 +570,114 @@
compatible = "qcom,vfe"; compatible = "qcom,vfe";
num_child = <2>; num_child = <2>;
}; };
cci: qcom,cci@ca0c000 {
cell-index = <0>;
compatible = "qcom,cci";
reg = <0xca0c000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg-names = "cci";
interrupts = <0 295 0>;
interrupt-names = "cci";
status = "ok";
mmagic-supply = <&gdsc_bimc_smmu>;
gdscr-supply = <&gdsc_camss_top>;
qcom,cam-vreg-name = "mmagic", "gdscr";
clocks = <&clock_mmss clk_mmss_camss_top_ahb_clk>,
<&clock_mmss clk_cci_clk_src>,
<&clock_mmss clk_mmss_camss_cci_ahb_clk>,
<&clock_mmss clk_mmss_camss_cci_clk>,
<&clock_mmss clk_mmss_camss_ahb_clk>;
clock-names = "camss_top_ahb_clk",
"cci_src_clk", "cci_ahb_clk", "camss_cci_clk",
"camss_ahb_clk";
qcom,clock-rates = <0 19200000 0 0 0>,
<0 37500000 0 0 0>;
pinctrl-names = "cci_default", "cci_suspend";
pinctrl-0 = <&cci0_active &cci1_active>;
pinctrl-1 = <&cci0_suspend &cci1_suspend>;
gpios = <&tlmm 17 0>,
<&tlmm 18 0>,
<&tlmm 19 0>,
<&tlmm 20 0>;
qcom,gpio-tbl-num = <0 1 2 3>;
qcom,gpio-tbl-flags = <1 1 1 1>;
qcom,gpio-tbl-label = "CCI_I2C_DATA0",
"CCI_I2C_CLK0",
"CCI_I2C_DATA1",
"CCI_I2C_CLK1";
i2c_freq_100Khz: qcom,i2c_standard_mode {
status = "disabled";
};
i2c_freq_400Khz: qcom,i2c_fast_mode {
status = "disabled";
};
i2c_freq_custom: qcom,i2c_custom_mode {
status = "disabled";
};
i2c_freq_1Mhz: qcom,i2c_fast_plus_mode {
status = "disabled";
};
};
};
&i2c_freq_100Khz {
qcom,hw-thigh = <201>;
qcom,hw-tlow = <174>;
qcom,hw-tsu-sto = <204>;
qcom,hw-tsu-sta = <231>;
qcom,hw-thd-dat = <22>;
qcom,hw-thd-sta = <162>;
qcom,hw-tbuf = <227>;
qcom,hw-scl-stretch-en = <0>;
qcom,hw-trdhld = <6>;
qcom,hw-tsp = <3>;
qcom,cci-clk-src = <37500000>;
status = "ok";
};
&i2c_freq_400Khz {
qcom,hw-thigh = <38>;
qcom,hw-tlow = <56>;
qcom,hw-tsu-sto = <40>;
qcom,hw-tsu-sta = <40>;
qcom,hw-thd-dat = <22>;
qcom,hw-thd-sta = <35>;
qcom,hw-tbuf = <62>;
qcom,hw-scl-stretch-en = <0>;
qcom,hw-trdhld = <6>;
qcom,hw-tsp = <3>;
qcom,cci-clk-src = <37500000>;
status = "ok";
};
&i2c_freq_custom {
qcom,hw-thigh = <38>;
qcom,hw-tlow = <56>;
qcom,hw-tsu-sto = <40>;
qcom,hw-tsu-sta = <40>;
qcom,hw-thd-dat = <22>;
qcom,hw-thd-sta = <35>;
qcom,hw-tbuf = <62>;
qcom,hw-scl-stretch-en = <1>;
qcom,hw-trdhld = <6>;
qcom,hw-tsp = <3>;
qcom,cci-clk-src = <37500000>;
status = "ok";
};
&i2c_freq_1Mhz {
qcom,hw-thigh = <16>;
qcom,hw-tlow = <22>;
qcom,hw-tsu-sto = <17>;
qcom,hw-tsu-sta = <18>;
qcom,hw-thd-dat = <16>;
qcom,hw-thd-sta = <15>;
qcom,hw-tbuf = <24>;
qcom,hw-scl-stretch-en = <0>;
qcom,hw-trdhld = <3>;
qcom,hw-tsp = <3>;
qcom,cci-clk-src = <37500000>;
status = "ok";
}; };

1
arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi
View file

@ -11,6 +11,7 @@
*/ */
#include "msmcobalt-pinctrl.dtsi" #include "msmcobalt-pinctrl.dtsi"
#include "msmcobalt-camera-sensor-cdp.dtsi"
/ { / {
bluetooth: bt_wcn3990 { bluetooth: bt_wcn3990 {
compatible = "qca,wcn3990"; compatible = "qca,wcn3990";

1
arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi
View file

@ -11,6 +11,7 @@
*/ */
#include "msmcobalt-pinctrl.dtsi" #include "msmcobalt-pinctrl.dtsi"
#include "msmcobalt-camera-sensor-mtp.dtsi"
/ { / {
bluetooth: bt_wcn3990 { bluetooth: bt_wcn3990 {
compatible = "qca,wcn3990"; compatible = "qca,wcn3990";

259
arch/arm/boot/dts/qcom/msmcobalt-pinctrl.dtsi
View file

@ -130,5 +130,264 @@
}; };
}; };
cci0_active: cci0_active {
mux {
/* CLK, DATA */
pins = "gpio17","gpio18"; // Only 2
function = "cci_i2c";
};
config {
pins = "gpio17","gpio18";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
};
};
cci0_suspend: cci0_suspend {
mux {
/* CLK, DATA */
pins = "gpio17","gpio18";
function = "cci_i2c";
};
config {
pins = "gpio17","gpio18";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cci1_active: cci1_active {
mux {
/* CLK, DATA */
pins = "gpio19","gpio20";
function = "cci_i2c";
};
config {
pins = "gpio19","gpio20";
bias-pull-up; /* PULL UP*/
drive-strength = <2>; /* 2 MA */
};
};
cci1_suspend: cci1_suspend {
mux {
/* CLK, DATA */
pins = "gpio19","gpio20";
function = "cci_i2c";
};
config {
pins = "gpio19","gpio20";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_actuator_vaf_active: cam_actuator_vaf_active {
/* ACTUATOR POWER */
mux {
pins = "gpio27";
function = "gpio";
};
config {
pins = "gpio27";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_actuator_vaf_suspend: cam_actuator_vaf_suspend {
/* ACTUATOR POWER */
mux {
pins = "gpio27";
function = "gpio";
};
config {
pins = "gpio27";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk0_active: cam_sensor_mclk0_active {
/* MCLK0 */
mux {
/* CLK, DATA */
pins = "gpio13";
function = "cam_mclk";
};
config {
pins = "gpio13";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
/* MCLK0 */
mux {
/* CLK, DATA */
pins = "gpio13";
function = "cam_mclk";
};
config {
pins = "gpio13";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_rear_active: cam_sensor_rear_active {
/* RESET, STANDBY */
mux {
pins = "gpio30","gpio29","gpio27";
function = "gpio";
};
config {
pins = "gpio30","gpio29","gpio27";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_rear_suspend: cam_sensor_rear_suspend {
/* RESET, STANDBY */
mux {
pins = "gpio30","gpio29","gpio27";
function = "gpio";
};
config {
pins = "gpio30","gpio29","gpio27";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk1_active: cam_sensor_mclk1_active {
/* MCLK1 */
mux {
/* CLK, DATA */
pins = "gpio14";
function = "cam_mclk";
};
config {
pins = "gpio14";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
/* MCLK1 */
mux {
/* CLK, DATA */
pins = "gpio14";
function = "cam_mclk";
};
config {
pins = "gpio14";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_rear2_active: cam_sensor_rear2_active {
/* RESET, STANDBY */
mux {
pins = "gpio63","gpio62";
function = "gpio";
};
config {
pins = "gpio63","gpio62";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_rear2_sus {
cam_sensor_rear2_suspend: cam_sensor_rear2_suspend {
/* RESET, STANDBY */
mux {
pins = "gpio63","gpio62";
function = "gpio";
};
config {
pins = "gpio63","gpio62";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
};
cam_sensor_mclk2_active: cam_sensor_mclk2_active {
/* MCLK1 */
mux {
/* CLK, DATA */
pins = "gpio15";
function = "cam_mclk";
};
config {
pins = "gpio15";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
/* MCLK1 */
mux {
/* CLK, DATA */
pins = "gpio15";
function = "cam_mclk";
};
config {
pins = "gpio15";
bias-pull-down; /* PULL DOWN */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_front_active: cam_sensor_front_active {
/* RESET, STANDBY */
mux {
pins = "gpio23","gpio26";
function = "gpio";
};
config {
pins = "gpio23","gpio26";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
cam_sensor_front_suspend: cam_sensor_front_suspend {
/* RESET, STANDBY */
mux {
pins = "gpio23","gpio26";
function = "gpio";
};
config {
pins = "gpio23","gpio26";
bias-disable; /* No PULL */
drive-strength = <2>; /* 2 MA */
};
};
}; };
}; };

7
drivers/media/platform/msm/camera_v2/sensor/csid/msm_csid.c
View file

@ -45,6 +45,7 @@
#define CSID_VERSION_V37 0x30070000 #define CSID_VERSION_V37 0x30070000
#define CSID_VERSION_V35 0x30050000 #define CSID_VERSION_V35 0x30050000
#define CSID_VERSION_V40 0x40000000 #define CSID_VERSION_V40 0x40000000
#define CSID_VERSION_V50 0x50000000
#define MSM_CSID_DRV_NAME "msm_csid" #define MSM_CSID_DRV_NAME "msm_csid"
#define DBG_CSID 0 #define DBG_CSID 0
@ -1135,6 +1136,12 @@ static int csid_probe(struct platform_device *pdev)
new_csid_dev->ctrl_reg->csid_lane_assign = new_csid_dev->ctrl_reg->csid_lane_assign =
csid_lane_assign_v3_5; csid_lane_assign_v3_5;
new_csid_dev->hw_dts_version = CSID_VERSION_V35; new_csid_dev->hw_dts_version = CSID_VERSION_V35;
} else if (of_device_is_compatible(new_csid_dev->pdev->dev.of_node,
"qcom,csid-v5.0")) {
new_csid_dev->ctrl_reg->csid_reg = csid_v3_5;
new_csid_dev->ctrl_reg->csid_lane_assign =
csid_lane_assign_v3_5;
new_csid_dev->hw_dts_version = CSID_VERSION_V50;
} else { } else {
pr_err("%s:%d, invalid hw version : 0x%x", __func__, __LINE__, pr_err("%s:%d, invalid hw version : 0x%x", __func__, __LINE__,
new_csid_dev->hw_dts_version); new_csid_dev->hw_dts_version);

103
drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_5_0_hwreg.h Normal file
View file

@ -0,0 +1,103 @@
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MSM_CSIPHY_5_0_HWREG_H
#define MSM_CSIPHY_5_0_HWREG_H
#define ULPM_WAKE_UP_TIMER_MODE 2
#define GLITCH_ELIMINATE_NUM 0x30
#include <sensor/csiphy/msm_csiphy.h>
struct csiphy_reg_parms_t csiphy_v5_0 = {
.mipi_csiphy_interrupt_status0_addr = 0x8B0,
.mipi_csiphy_interrupt_clear0_addr = 0x858,
.mipi_csiphy_glbl_irq_cmd_addr = 0x828,
.combo_clk_mask = 0x10,
};
struct csiphy_reg_3ph_parms_t csiphy_v5_0_3ph = {
/*MIPI CSI PHY registers*/
{0x814, 0x2A},
{0x818, 0x1},
{0x188, 0x7F},
{0x18C, 0x7F},
{0x190, 0x0},
{0x104, 0x6},
{0x108, 0x1},
{0x10c, 0x12},
{0x114, 0x20},
{0x118, 0x3E},
{0x11c, 0x41},
{0x120, 0x41},
{0x124, 0x7F},
{0x128, 0x0},
{0x12c, 0x0},
{0x130, 0x1},
{0x134, 0x0},
{0x138, 0x0},
{0x13C, 0x10},
{0x140, 0x1},
{0x144, GLITCH_ELIMINATE_NUM},
{0x148, 0xFE},
{0x14C, 0x1},
{0x154, 0x0},
{0x15C, 0x3},
{0x160, ULPM_WAKE_UP_TIMER_MODE},
{0x164, 0x00},
{0x168, 0xA0},
{0x16C, 0x25},
{0x170, 0x41},
{0x174, 0x41},
{0x178, 0x3E},
{0x17C, 0x0},
{0x180, 0x0},
{0x184, 0x7F},
{0x1cc, 0x41},
{0x81c, 0x1},
{0x82c, 0xFF},
{0x830, 0xFF},
{0x834, 0xFB},
{0x838, 0xFF},
{0x83c, 0x7F},
{0x840, 0xFF},
{0x844, 0xFF},
{0x848, 0xEF},
{0x84c, 0xFF},
{0x850, 0xFF},
{0x854, 0xFF},
{0x28, 0x0},
{0x800, 0x0},
{0x4, 0x8},
{0x8, 0x4},
{0x8, 0x4},
{0x10, 0x52},
{0x14, 0x60},
{0x14, 0x60},
{0x1C, 0xa},
{0x1c, 0xa},
{0x38, 0x1},
{0x3C, 0xB8},
{0x3C, 0xB8},
{0x14, 0x0},
{0x0, 0x0},
{0x700, 0xC0},
{0x150, 0},
{0x1dc, 0x1},
{0x2C, 0x1},
{0x34, 0xf},
{0x728, 0x4},
{0x0, 0x91},
{0x70C, 0x16},
{0x38, 0xFE},
};
#endif

262
drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c
View file

@ -25,6 +25,7 @@
#include "include/msm_csiphy_3_2_hwreg.h" #include "include/msm_csiphy_3_2_hwreg.h"
#include "include/msm_csiphy_3_4_2_hwreg.h" #include "include/msm_csiphy_3_4_2_hwreg.h"
#include "include/msm_csiphy_3_5_hwreg.h" #include "include/msm_csiphy_3_5_hwreg.h"
#include "include/msm_csiphy_5_0_hwreg.h"
#include "cam_hw_ops.h" #include "cam_hw_ops.h"
#define DBG_CSIPHY 0 #define DBG_CSIPHY 0
@ -39,6 +40,7 @@
#define CSIPHY_VERSION_V32 0x32 #define CSIPHY_VERSION_V32 0x32
#define CSIPHY_VERSION_V342 0x342 #define CSIPHY_VERSION_V342 0x342
#define CSIPHY_VERSION_V35 0x35 #define CSIPHY_VERSION_V35 0x35
#define CSIPHY_VERSION_V50 0x50
#define MSM_CSIPHY_DRV_NAME "msm_csiphy" #define MSM_CSIPHY_DRV_NAME "msm_csiphy"
#define CLK_LANE_OFFSET 1 #define CLK_LANE_OFFSET 1
#define NUM_LANES_OFFSET 4 #define NUM_LANES_OFFSET 4
@ -283,6 +285,129 @@ static int msm_csiphy_3phase_lane_config(
return 0; return 0;
} }
static int msm_csiphy_3phase_lane_config_v50(
struct csiphy_device *csiphy_dev,
struct msm_camera_csiphy_params *csiphy_params)
{
uint8_t i = 0;
uint16_t lane_mask = 0, lane_enable = 0, temp;
void __iomem *csiphybase;
csiphybase = csiphy_dev->base;
lane_mask = csiphy_params->lane_mask & 0x7;
while (lane_mask != 0) {
temp = (i << 1)+1;
lane_enable |= ((lane_mask & 0x1) << temp);
lane_mask >>= 1;
i++;
}
msm_camera_io_w(lane_enable,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_cmn_ctrl5.addr);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_cmn_ctrl6.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_cmn_ctrl6.addr);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_cmn_ctrl7.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_cmn_ctrl7.addr);
lane_mask = csiphy_params->lane_mask & 0x7;
i = 0;
while (lane_mask & 0x7) {
if (!(lane_mask & 0x1)) {
i++;
lane_mask >>= 1;
continue;
}
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl23.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl23.addr + 0x200*i);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl26.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl26.addr + 0x200*i);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl27.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl27.addr + 0x200*i);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl1.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl1.addr + 0x200*i);
msm_camera_io_w((csiphy_params->settle_cnt & 0xff),
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl3.addr + 0x200*i);
msm_camera_io_w(((csiphy_params->settle_cnt >> 8) & 0xff),
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl2.addr + 0x200*i);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl5.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl5.addr + 0x200*i);
msm_camera_io_w(((csiphy_params->settle_cnt >> 8) & 0xff),
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl20.addr + 0x200*i);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl6.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl6.addr + 0x200*i);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl7.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl7.addr + 0x200*i);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl8.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl8.addr + 0x200*i);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl9.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl9.addr + 0x200*i);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl10.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl10.addr + 0x200*i);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl11.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl11.addr + 0x200*i);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl17.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl17.addr + 0x200*i);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl24.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl24.addr + 0x200*i);
if (ULPM_WAKE_UP_TIMER_MODE == 0x22) {
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl51.data,
csiphybase + csiphy_dev->ctrl_reg->
csiphy_3ph_reg.mipi_csiphy_3ph_lnn_ctrl51.addr +
0x200*i);
}
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl25.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl25.addr + 0x200*i);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl55.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_lnn_ctrl55.addr + 0x200*i);
lane_mask >>= 1;
i++;
}
/* Delay for stabilizing the regulator*/
usleep_range(10, 15);
msm_csiphy_cphy_irq_config(csiphy_dev, csiphy_params);
return 0;
}
static int msm_csiphy_2phase_lane_config( static int msm_csiphy_2phase_lane_config(
struct csiphy_device *csiphy_dev, struct csiphy_device *csiphy_dev,
struct msm_camera_csiphy_params *csiphy_params) struct msm_camera_csiphy_params *csiphy_params)
@ -433,6 +558,119 @@ static int msm_csiphy_2phase_lane_config(
return 0; return 0;
} }
static int msm_csiphy_2phase_lane_config_v50(
struct csiphy_device *csiphy_dev,
struct msm_camera_csiphy_params *csiphy_params)
{
uint32_t val = 0, lane_enable = 0, clk_lane, mask = 1;
uint16_t lane_mask = 0, i = 0, offset;
void __iomem *csiphybase;
csiphybase = csiphy_dev->base;
lane_mask = csiphy_params->lane_mask & 0x1f;
for (i = 0; i < MAX_LANES; i++) {
if (mask == 0x2) {
if (lane_mask & mask)
lane_enable |= 0x80;
i--;
} else if (lane_mask & mask)
lane_enable |= 0x1 << (i<<1);
mask <<= 1;
}
CDBG("%s:%d lane_enable: %d\n", __func__, __LINE__, lane_enable);
msm_camera_io_w(lane_enable,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_cmn_ctrl5.addr);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_cmn_ctrl6.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_cmn_ctrl6.addr);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_cmn_ctrl7.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_3ph_cmn_ctrl7.addr);
for (i = 0, mask = 0x1; i < MAX_LANES; i++) {
if (!(lane_mask & mask)) {
if (mask == 0x2)
i--;
mask <<= 0x1;
continue;
}
if (mask == 0x2) {
val = 4;
offset = CLOCK_OFFSET;
clk_lane = 1;
i--;
} else {
offset = 0x200*i;
val = 0;
clk_lane = 0;
}
if (csiphy_params->combo_mode == 1) {
val |= 0xA;
if (mask == csiphy_dev->ctrl_reg->
csiphy_reg.combo_clk_mask) {
val |= 0x4;
clk_lane = 1;
}
}
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_ctrl11.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_ctrl11.addr + offset);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_ctrl13.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_ctrl13.addr + offset);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_cfg7.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_cfg7.addr + offset);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_cfg5.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_cfg5.addr + offset);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnck_ctrl10.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnck_ctrl10.addr);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_ctrl15.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_ctrl15.addr + offset);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_ctrl0.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_ctrl0.addr + offset);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_cfg1.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_cfg1.addr + offset);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_cfg2.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_cfg2.addr + offset);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnck_ctrl3.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnck_ctrl3.addr);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_cfg4.data, csiphybase +
csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_cfg4.addr + offset);
msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_ctrl14.data,
csiphybase + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_ctrl14.addr + offset);
mask <<= 1;
}
msm_csiphy_cphy_irq_config(csiphy_dev, csiphy_params);
return 0;
}
static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev, static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev,
struct msm_camera_csiphy_params *csiphy_params) struct msm_camera_csiphy_params *csiphy_params)
{ {
@ -486,7 +724,9 @@ static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev,
__func__, csiphy_params->settle_cnt, __func__, csiphy_params->settle_cnt,
csiphy_params->csid_core); csiphy_params->csid_core);
if (csiphy_dev->hw_version >= CSIPHY_VERSION_V30) { if (csiphy_dev->hw_version >= CSIPHY_VERSION_V30 &&
csiphy_dev->clk_mux_base != NULL &&
csiphy_dev->hw_version != CSIPHY_VERSION_V50) {
val = msm_camera_io_r(csiphy_dev->clk_mux_base); val = msm_camera_io_r(csiphy_dev->clk_mux_base);
if (csiphy_params->combo_mode && if (csiphy_params->combo_mode &&
(csiphy_params->lane_mask & 0x18) == 0x18) { (csiphy_params->lane_mask & 0x18) == 0x18) {
@ -509,10 +749,18 @@ static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev,
rc = msm_camera_clk_enable(&csiphy_dev->pdev->dev, rc = msm_camera_clk_enable(&csiphy_dev->pdev->dev,
csiphy_dev->csiphy_3p_clk_info, csiphy_dev->csiphy_3p_clk_info,
csiphy_dev->csiphy_3p_clk, 2, true); csiphy_dev->csiphy_3p_clk, 2, true);
if (csiphy_dev->hw_dts_version == CSIPHY_VERSION_V50)
rc = msm_csiphy_3phase_lane_config_v50(
csiphy_dev, csiphy_params);
else
rc = msm_csiphy_3phase_lane_config(csiphy_dev, rc = msm_csiphy_3phase_lane_config(csiphy_dev,
csiphy_params); csiphy_params);
csiphy_dev->num_irq_registers = 20; csiphy_dev->num_irq_registers = 20;
} else { } else {
if (csiphy_dev->hw_dts_version == CSIPHY_VERSION_V50)
rc = msm_csiphy_2phase_lane_config_v50(
csiphy_dev, csiphy_params);
else
rc = msm_csiphy_2phase_lane_config(csiphy_dev, rc = msm_csiphy_2phase_lane_config(csiphy_dev,
csiphy_params); csiphy_params);
csiphy_dev->num_irq_registers = 11; csiphy_dev->num_irq_registers = 11;
@ -1340,6 +1588,12 @@ static int csiphy_probe(struct platform_device *pdev)
new_csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v3_5; new_csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v3_5;
new_csiphy_dev->hw_dts_version = CSIPHY_VERSION_V35; new_csiphy_dev->hw_dts_version = CSIPHY_VERSION_V35;
new_csiphy_dev->csiphy_3phase = CSI_3PHASE_HW; new_csiphy_dev->csiphy_3phase = CSI_3PHASE_HW;
} else if (of_device_is_compatible(new_csiphy_dev->pdev->dev.of_node,
"qcom,csiphy-v5.0")) {
new_csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_v5_0_3ph;
new_csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v5_0;
new_csiphy_dev->hw_dts_version = CSIPHY_VERSION_V50;
new_csiphy_dev->csiphy_3phase = CSI_3PHASE_HW;
} else { } else {
pr_err("%s:%d, invalid hw version : 0x%x\n", __func__, __LINE__, pr_err("%s:%d, invalid hw version : 0x%x\n", __func__, __LINE__,
new_csiphy_dev->hw_dts_version); new_csiphy_dev->hw_dts_version);
@ -1365,11 +1619,8 @@ static int csiphy_probe(struct platform_device *pdev)
if (new_csiphy_dev->hw_dts_version >= CSIPHY_VERSION_V30) { if (new_csiphy_dev->hw_dts_version >= CSIPHY_VERSION_V30) {
new_csiphy_dev->clk_mux_base = msm_camera_get_reg_base(pdev, new_csiphy_dev->clk_mux_base = msm_camera_get_reg_base(pdev,
"csiphy_clk_mux", true); "csiphy_clk_mux", true);
if (!new_csiphy_dev->clk_mux_base) { if (!new_csiphy_dev->clk_mux_base)
pr_err("%s: no mem resource?\n", __func__); pr_err("%s: no mem resource?\n", __func__);
rc = -ENODEV;
goto csiphy_no_mux_resource;
}
} }
new_csiphy_dev->irq = msm_camera_get_irq(pdev, "csiphy"); new_csiphy_dev->irq = msm_camera_get_irq(pdev, "csiphy");
if (!new_csiphy_dev->irq) { if (!new_csiphy_dev->irq) {
@ -1401,7 +1652,6 @@ csiphy_no_irq_resource:
msm_camera_put_reg_base(pdev, new_csiphy_dev->clk_mux_base, msm_camera_put_reg_base(pdev, new_csiphy_dev->clk_mux_base,
"csiphy_clk_mux", true); "csiphy_clk_mux", true);
} }
csiphy_no_mux_resource:
msm_camera_put_reg_base(pdev, new_csiphy_dev->base, "csiphy", true); msm_camera_put_reg_base(pdev, new_csiphy_dev->base, "csiphy", true);
csiphy_no_resource: csiphy_no_resource:
mutex_destroy(&new_csiphy_dev->mutex); mutex_destroy(&new_csiphy_dev->mutex);

8
drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h
View file

@ -126,6 +126,14 @@ struct csiphy_reg_3ph_parms_t {
struct csiphy_reg_t mipi_csiphy_2ph_lnn_test_force; struct csiphy_reg_t mipi_csiphy_2ph_lnn_test_force;
struct csiphy_reg_t mipi_csiphy_2ph_lnn_ctrl5; struct csiphy_reg_t mipi_csiphy_2ph_lnn_ctrl5;
struct csiphy_reg_t mipi_csiphy_3ph_lnck_cfg1; struct csiphy_reg_t mipi_csiphy_3ph_lnck_cfg1;
struct csiphy_reg_t mipi_csiphy_3ph_lnn_ctrl20;
struct csiphy_reg_t mipi_csiphy_3ph_lnn_ctrl55;
struct csiphy_reg_t mipi_csiphy_2ph_lnn_ctrl11;
struct csiphy_reg_t mipi_csiphy_2ph_lnn_ctrl13;
struct csiphy_reg_t mipi_csiphy_2ph_lnck_ctrl10;
struct csiphy_reg_t mipi_csiphy_2ph_lnn_ctrl0;
struct csiphy_reg_t mipi_csiphy_2ph_lnck_ctrl3;
struct csiphy_reg_t mipi_csiphy_2ph_lnn_ctrl14;
}; };
struct csiphy_ctrl_t { struct csiphy_ctrl_t {