Merge "ath10k: define structure for the copy engine misc regs"
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ea58c08a4d
8 changed files with 520 additions and 414 deletions
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@ -64,7 +64,8 @@ static inline void ath10k_ce_dest_ring_write_index_set(struct ath10k *ar,
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n);
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ar_opaque->bus_ops->write32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->dst_wr_index_addr, n);
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}
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static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar,
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@ -72,8 +73,8 @@ static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar,
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
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DST_WR_INDEX_ADDRESS);
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return ar_opaque->bus_ops->read32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->dst_wr_index_addr);
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}
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static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar,
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@ -82,7 +83,8 @@ static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar,
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n);
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ar_opaque->bus_ops->write32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->sr_wr_index_addr, n);
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}
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static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar,
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@ -90,8 +92,8 @@ static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar,
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
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SR_WR_INDEX_ADDRESS);
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return ar_opaque->bus_ops->read32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->sr_wr_index_addr);
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}
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static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,
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@ -99,8 +101,8 @@ static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
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CURRENT_SRRI_ADDRESS);
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return ar_opaque->bus_ops->read32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->current_srri_addr);
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}
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static inline void ath10k_ce_shadow_src_ring_write_index_set(struct ath10k *ar,
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@ -130,7 +132,8 @@ static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar,
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr);
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ar_opaque->bus_ops->write32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->sr_base_addr, addr);
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}
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static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar,
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@ -139,7 +142,8 @@ static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar,
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n);
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ar_opaque->bus_ops->write32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->sr_size_addr, n);
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}
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static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar,
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@ -147,12 +151,14 @@ static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar,
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unsigned int n)
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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u32 ctrl1_addr = ar_opaque->bus_ops->read32((ar),
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(ce_ctrl_addr) + CE_CTRL1_ADDRESS);
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struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
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(ctrl1_addr & ~CE_CTRL1_DMAX_LENGTH_MASK) |
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CE_CTRL1_DMAX_LENGTH_SET(n));
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u32 ctrl1_addr = ar_opaque->bus_ops->read32((ar),
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(ce_ctrl_addr) + ctrl_regs->addr);
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + ctrl_regs->addr,
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(ctrl1_addr & ~(ctrl_regs->dmax->mask)) |
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ctrl_regs->dmax->set(n, ctrl_regs->dmax));
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}
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static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar,
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@ -160,12 +166,14 @@ static inline void ath10k_ce_src_ring_byte_swap_set(struct ath10k *ar,
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unsigned int n)
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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u32 ctrl1_addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
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CE_CTRL1_ADDRESS);
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struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
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(ctrl1_addr & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) |
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CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n));
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u32 ctrl1_addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
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ctrl_regs->addr);
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + ctrl_regs->addr,
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(ctrl1_addr & ~(ctrl_regs->src_ring->mask)) |
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ctrl_regs->src_ring->set(n, ctrl_regs->src_ring));
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}
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static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar,
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@ -173,12 +181,14 @@ static inline void ath10k_ce_dest_ring_byte_swap_set(struct ath10k *ar,
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unsigned int n)
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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u32 ctrl1_addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
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CE_CTRL1_ADDRESS);
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struct ath10k_hw_ce_ctrl1 *ctrl_regs = ar->hw_ce_regs->ctrl1_regs;
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + CE_CTRL1_ADDRESS,
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(ctrl1_addr & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) |
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CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n));
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u32 ctrl1_addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
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ctrl_regs->addr);
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + ctrl_regs->addr,
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(ctrl1_addr & ~(ctrl_regs->dst_ring->mask)) |
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ctrl_regs->dst_ring->set(n, ctrl_regs->dst_ring));
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}
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static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar,
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@ -186,8 +196,8 @@ static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar,
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
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CURRENT_DRRI_ADDRESS);
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return ar_opaque->bus_ops->read32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->current_drri_addr);
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}
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static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,
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@ -196,7 +206,8 @@ static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr);
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ar_opaque->bus_ops->write32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->dr_base_addr, addr);
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}
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static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar,
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@ -205,7 +216,8 @@ static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar,
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n);
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ar_opaque->bus_ops->write32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->dr_size_addr, n);
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}
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static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar,
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@ -213,13 +225,12 @@ static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar,
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unsigned int n)
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;
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u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + srcr_wm->addr);
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u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
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SRC_WATERMARK_ADDRESS);
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,
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(addr & ~SRC_WATERMARK_HIGH_MASK) |
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SRC_WATERMARK_HIGH_SET(n));
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + srcr_wm->addr,
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(addr & ~(srcr_wm->wm_high->mask)) |
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(srcr_wm->wm_high->set(n, srcr_wm->wm_high)));
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}
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static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar,
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@ -227,12 +238,12 @@ static inline void ath10k_ce_src_ring_lowmark_set(struct ath10k *ar,
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unsigned int n)
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
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SRC_WATERMARK_ADDRESS);
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struct ath10k_hw_ce_dst_src_wm_regs *srcr_wm = ar->hw_ce_regs->wm_srcr;
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u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + srcr_wm->addr);
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SRC_WATERMARK_ADDRESS,
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(addr & ~SRC_WATERMARK_LOW_MASK) |
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SRC_WATERMARK_LOW_SET(n));
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + srcr_wm->addr,
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(addr & ~(srcr_wm->wm_low->mask)) |
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(srcr_wm->wm_low->set(n, srcr_wm->wm_low)));
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}
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static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar,
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@ -240,12 +251,12 @@ static inline void ath10k_ce_dest_ring_highmark_set(struct ath10k *ar,
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unsigned int n)
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
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DST_WATERMARK_ADDRESS);
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struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;
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u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + dstr_wm->addr);
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,
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(addr & ~DST_WATERMARK_HIGH_MASK) |
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DST_WATERMARK_HIGH_SET(n));
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + dstr_wm->addr,
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(addr & ~(dstr_wm->wm_high->mask)) |
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(dstr_wm->wm_high->set(n, dstr_wm->wm_high)));
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}
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static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar,
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@ -253,67 +264,82 @@ static inline void ath10k_ce_dest_ring_lowmark_set(struct ath10k *ar,
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unsigned int n)
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
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DST_WATERMARK_ADDRESS);
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struct ath10k_hw_ce_dst_src_wm_regs *dstr_wm = ar->hw_ce_regs->wm_dstr;
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u32 addr = ar_opaque->bus_ops->read32(ar, ce_ctrl_addr + dstr_wm->addr);
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DST_WATERMARK_ADDRESS,
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(addr & ~DST_WATERMARK_LOW_MASK) |
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DST_WATERMARK_LOW_SET(n));
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + dstr_wm->addr,
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(addr & ~(dstr_wm->wm_low->mask)) |
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(dstr_wm->wm_low->set(n, dstr_wm->wm_low)));
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}
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static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,
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ce_ctrl_addr + HOST_IE_ADDRESS);
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struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
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host_ie_addr | HOST_IE_COPY_COMPLETE_MASK);
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u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr);
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ar_opaque->bus_ops->write32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,
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host_ie_addr | host_ie->copy_complete->mask);
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}
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static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,
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ce_ctrl_addr + HOST_IE_ADDRESS);
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struct ath10k_hw_ce_host_ie *host_ie = ar->hw_ce_regs->host_ie;
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
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host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK);
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u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr);
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ar_opaque->bus_ops->write32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,
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host_ie_addr & ~(host_ie->copy_complete->mask));
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}
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static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,
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ce_ctrl_addr + HOST_IE_ADDRESS);
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struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
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host_ie_addr & ~CE_WATERMARK_MASK);
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u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr);
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ar_opaque->bus_ops->write32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,
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host_ie_addr & ~(wm_regs->wm_mask));
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}
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static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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u32 misc_ie_addr = ar_opaque->bus_ops->read32(ar,
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ce_ctrl_addr + MISC_IE_ADDRESS);
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struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,
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misc_ie_addr | CE_ERROR_MASK);
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u32 misc_ie_addr = ar_opaque->bus_ops->read32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr);
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ar_opaque->bus_ops->write32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,
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misc_ie_addr | misc_regs->err_mask);
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}
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static inline void ath10k_ce_error_intr_disable(struct ath10k *ar,
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u32 ce_ctrl_addr)
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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u32 misc_ie_addr = ar_opaque->bus_ops->read32(ar,
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ce_ctrl_addr + MISC_IE_ADDRESS);
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struct ath10k_hw_ce_misc_regs *misc_regs = ar->hw_ce_regs->misc_regs;
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,
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misc_ie_addr & ~CE_ERROR_MASK);
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u32 misc_ie_addr = ar_opaque->bus_ops->read32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr);
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ar_opaque->bus_ops->write32(ar,
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ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,
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misc_ie_addr & ~(misc_regs->err_mask));
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}
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static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
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@ -321,8 +347,9 @@ static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
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unsigned int mask)
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{
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struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
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struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
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ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IS_ADDRESS, mask);
|
||||
ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + wm_regs->addr, mask);
|
||||
}
|
||||
|
||||
u32 shadow_sr_wr_ind_addr(struct ath10k *ar, u32 ctrl_addr)
|
||||
|
|
@ -391,6 +418,21 @@ u32 shadow_dst_wr_ind_addr(struct ath10k *ar, u32 ctrl_addr)
|
|||
return addr;
|
||||
}
|
||||
|
||||
static inline void ath10k_ce_snoc_addr_config(struct ce_desc *sdesc,
|
||||
dma_addr_t buffer,
|
||||
unsigned int flags)
|
||||
{
|
||||
__le32 *addr = (__le32 *)&sdesc->addr;
|
||||
|
||||
flags |= upper_32_bits(buffer) & CE_DESC_FLAGS_GET_MASK;
|
||||
addr[0] = __cpu_to_le32(buffer);
|
||||
addr[1] = flags;
|
||||
if (flags & CE_SEND_FLAG_GATHER)
|
||||
addr[1] |= CE_WCN3990_DESC_FLAGS_GATHER;
|
||||
else
|
||||
addr[1] &= ~CE_WCN3990_DESC_FLAGS_GATHER;
|
||||
}
|
||||
|
||||
/*
|
||||
* Guts of ath10k_ce_send, used by both ath10k_ce_send and
|
||||
* ath10k_ce_sendlist_send.
|
||||
|
|
@ -434,17 +476,10 @@ int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
|
|||
if (flags & CE_SEND_FLAG_BYTE_SWAP)
|
||||
desc_flags |= CE_DESC_FLAGS_BYTE_SWAP;
|
||||
|
||||
if (QCA_REV_WCN3990(ar)) {
|
||||
flags |= upper_32_bits(buffer) & CE_DESC_FLAGS_GET_MASK;
|
||||
sdesc.addr_lo = __cpu_to_le32(buffer);
|
||||
sdesc.addr_hi = flags;
|
||||
if (flags & CE_SEND_FLAG_GATHER)
|
||||
sdesc.addr_hi |= CE_WCN3990_DESC_FLAGS_GATHER;
|
||||
if (QCA_REV_WCN3990(ar))
|
||||
ath10k_ce_snoc_addr_config(&sdesc, buffer, flags);
|
||||
else
|
||||
sdesc.addr_hi &= ~CE_WCN3990_DESC_FLAGS_GATHER;
|
||||
} else {
|
||||
sdesc.addr = __cpu_to_le32(buffer);
|
||||
}
|
||||
|
||||
sdesc.nbytes = __cpu_to_le16(nbytes);
|
||||
sdesc.flags = __cpu_to_le16(desc_flags);
|
||||
|
|
@ -866,13 +901,14 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
|
|||
{
|
||||
struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
|
||||
struct ath10k_ce_pipe *ce_state = &ar_opaque->ce_states[ce_id];
|
||||
struct ath10k_hw_ce_host_wm_regs *wm_regs = ar->hw_ce_regs->wm_regs;
|
||||
u32 ctrl_addr = ce_state->ctrl_addr;
|
||||
|
||||
spin_lock_bh(&ar_opaque->ce_lock);
|
||||
|
||||
/* Clear the copy-complete interrupts that will be handled here. */
|
||||
ath10k_ce_engine_int_status_clear(ar, ctrl_addr,
|
||||
HOST_IS_COPY_COMPLETE_MASK);
|
||||
wm_regs->cc_mask);
|
||||
|
||||
spin_unlock_bh(&ar_opaque->ce_lock);
|
||||
|
||||
|
|
@ -888,7 +924,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
|
|||
* Misc CE interrupts are not being handled, but still need
|
||||
* to be cleared.
|
||||
*/
|
||||
ath10k_ce_engine_int_status_clear(ar, ctrl_addr, CE_WATERMARK_MASK);
|
||||
ath10k_ce_engine_int_status_clear(ar, ctrl_addr, wm_regs->wm_mask);
|
||||
|
||||
spin_unlock_bh(&ar_opaque->ce_lock);
|
||||
}
|
||||
|
|
@ -983,7 +1019,7 @@ void ath10k_ce_enable_per_ce_interrupts(struct ath10k *ar, unsigned int ce_id)
|
|||
u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id);
|
||||
struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
|
||||
|
||||
offset = HOST_IE_ADDRESS + ctrl_addr;
|
||||
offset = ar->hw_ce_regs->host_ie_addr + ctrl_addr;
|
||||
ar_opaque->bus_ops->write32(ar, offset, 1);
|
||||
ar_opaque->bus_ops->read32(ar, offset);
|
||||
}
|
||||
|
|
@ -994,7 +1030,7 @@ void ath10k_ce_disable_per_ce_interrupts(struct ath10k *ar, unsigned int ce_id)
|
|||
u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id);
|
||||
struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
|
||||
|
||||
offset = HOST_IE_ADDRESS + ctrl_addr;
|
||||
offset = ar->hw_ce_regs->host_ie_addr + ctrl_addr;
|
||||
ar_opaque->bus_ops->write32(ar, offset, 0);
|
||||
ar_opaque->bus_ops->read32(ar, offset);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -58,13 +58,7 @@ struct ce_desc {
|
|||
};
|
||||
#else
|
||||
struct ce_desc {
|
||||
union {
|
||||
__le64 addr;
|
||||
struct {
|
||||
__le32 addr_lo;
|
||||
__le32 addr_hi;
|
||||
};
|
||||
};
|
||||
u16 nbytes; /* length in register map */
|
||||
u16 flags; /* fw_metadata_high */
|
||||
u32 toeplitz_hash_result;
|
||||
|
|
@ -362,311 +356,6 @@ struct ce_attr {
|
|||
void (*recv_cb)(struct ath10k_ce_pipe *);
|
||||
};
|
||||
|
||||
#ifndef CONFIG_ATH10K_SNOC
|
||||
#define SR_BA_ADDRESS 0x0000
|
||||
#define SR_SIZE_ADDRESS 0x0004
|
||||
#define DR_BA_ADDRESS 0x0008
|
||||
#define DR_SIZE_ADDRESS 0x000c
|
||||
#define CE_CMD_ADDRESS 0x0018
|
||||
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB 17
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \
|
||||
(((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
|
||||
CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
|
||||
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB 16
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \
|
||||
(((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \
|
||||
CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \
|
||||
(((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
|
||||
CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
|
||||
|
||||
#define CE_CTRL1_DMAX_LENGTH_MSB 15
|
||||
#define CE_CTRL1_DMAX_LENGTH_LSB 0
|
||||
#define CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
|
||||
#define CE_CTRL1_DMAX_LENGTH_GET(x) \
|
||||
(((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB)
|
||||
#define CE_CTRL1_DMAX_LENGTH_SET(x) \
|
||||
(((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
|
||||
|
||||
#define CE_CTRL1_ADDRESS 0x0010
|
||||
#define CE_CTRL1_HW_MASK 0x0007ffff
|
||||
#define CE_CTRL1_SW_MASK 0x0007ffff
|
||||
#define CE_CTRL1_HW_WRITE_MASK 0x00000000
|
||||
#define CE_CTRL1_SW_WRITE_MASK 0x0007ffff
|
||||
#define CE_CTRL1_RSTMASK 0xffffffff
|
||||
#define CE_CTRL1_RESET 0x00000080
|
||||
|
||||
#define CE_CMD_HALT_STATUS_MSB 3
|
||||
#define CE_CMD_HALT_STATUS_LSB 3
|
||||
#define CE_CMD_HALT_STATUS_MASK 0x00000008
|
||||
#define CE_CMD_HALT_STATUS_GET(x) \
|
||||
(((x) & CE_CMD_HALT_STATUS_MASK) >> CE_CMD_HALT_STATUS_LSB)
|
||||
#define CE_CMD_HALT_STATUS_SET(x) \
|
||||
(((0 | (x)) << CE_CMD_HALT_STATUS_LSB) & CE_CMD_HALT_STATUS_MASK)
|
||||
#define CE_CMD_HALT_STATUS_RESET 0
|
||||
#define CE_CMD_HALT_MSB 0
|
||||
#define CE_CMD_HALT_MASK 0x00000001
|
||||
|
||||
#define HOST_IE_COPY_COMPLETE_MSB 0
|
||||
#define HOST_IE_COPY_COMPLETE_LSB 0
|
||||
#define HOST_IE_COPY_COMPLETE_MASK 0x00000001
|
||||
#define HOST_IE_COPY_COMPLETE_GET(x) \
|
||||
(((x) & HOST_IE_COPY_COMPLETE_MASK) >> HOST_IE_COPY_COMPLETE_LSB)
|
||||
#define HOST_IE_COPY_COMPLETE_SET(x) \
|
||||
(((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK)
|
||||
#define HOST_IE_COPY_COMPLETE_RESET 0
|
||||
#define HOST_IE_ADDRESS 0x002c
|
||||
|
||||
#define HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
|
||||
#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008
|
||||
#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004
|
||||
#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002
|
||||
#define HOST_IS_COPY_COMPLETE_MASK 0x00000001
|
||||
#define HOST_IS_ADDRESS 0x0030
|
||||
|
||||
#define MISC_IE_ADDRESS 0x0034
|
||||
|
||||
#define MISC_IS_AXI_ERR_MASK 0x00000400
|
||||
|
||||
#define MISC_IS_DST_ADDR_ERR_MASK 0x00000200
|
||||
#define MISC_IS_SRC_LEN_ERR_MASK 0x00000100
|
||||
#define MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080
|
||||
#define MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040
|
||||
#define MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020
|
||||
|
||||
#define MISC_IS_ADDRESS 0x0038
|
||||
|
||||
#define SR_WR_INDEX_ADDRESS 0x003c
|
||||
|
||||
#define DST_WR_INDEX_ADDRESS 0x0040
|
||||
|
||||
#define CURRENT_SRRI_ADDRESS 0x0044
|
||||
|
||||
#define CURRENT_DRRI_ADDRESS 0x0048
|
||||
|
||||
#define SRC_WATERMARK_LOW_MSB 31
|
||||
#define SRC_WATERMARK_LOW_LSB 16
|
||||
#define SRC_WATERMARK_LOW_MASK 0xffff0000
|
||||
#define SRC_WATERMARK_LOW_GET(x) \
|
||||
(((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB)
|
||||
#define SRC_WATERMARK_LOW_SET(x) \
|
||||
(((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
|
||||
#define SRC_WATERMARK_LOW_RESET 0
|
||||
#define SRC_WATERMARK_HIGH_MSB 15
|
||||
#define SRC_WATERMARK_HIGH_LSB 0
|
||||
#define SRC_WATERMARK_HIGH_MASK 0x0000ffff
|
||||
#define SRC_WATERMARK_HIGH_GET(x) \
|
||||
(((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB)
|
||||
#define SRC_WATERMARK_HIGH_SET(x) \
|
||||
(((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
|
||||
#define SRC_WATERMARK_HIGH_RESET 0
|
||||
#define SRC_WATERMARK_ADDRESS 0x004c
|
||||
|
||||
#define DST_WATERMARK_LOW_LSB 16
|
||||
#define DST_WATERMARK_LOW_MASK 0xffff0000
|
||||
#define DST_WATERMARK_LOW_SET(x) \
|
||||
(((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
|
||||
#define DST_WATERMARK_LOW_RESET 0
|
||||
#define DST_WATERMARK_HIGH_MSB 15
|
||||
#define DST_WATERMARK_HIGH_LSB 0
|
||||
#define DST_WATERMARK_HIGH_MASK 0x0000ffff
|
||||
#define DST_WATERMARK_HIGH_GET(x) \
|
||||
(((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB)
|
||||
#define DST_WATERMARK_HIGH_SET(x) \
|
||||
(((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
|
||||
#define DST_WATERMARK_HIGH_RESET 0
|
||||
#define DST_WATERMARK_ADDRESS 0x0050
|
||||
|
||||
#else
|
||||
#define WCN3990_CE0_SR_BA_LOW (0x00240000)
|
||||
#define WCN3990_CE1_SR_BA_LOW (0x00241000)
|
||||
#define WCN3990_CE2_SR_BA_LOW (0x00242000)
|
||||
#define WCN3990_CE3_SR_BA_LOW (0x00243000)
|
||||
#define WCN3990_CE4_SR_BA_LOW (0x00244000)
|
||||
#define WCN3990_CE5_SR_BA_LOW (0x00245000)
|
||||
#define WCN3990_CE6_SR_BA_LOW (0x00246000)
|
||||
#define WCN3990_CE7_SR_BA_LOW (0x00247000)
|
||||
#define WCN3990_CE8_SR_BA_LOW (0x00248000)
|
||||
#define WCN3990_CE9_SR_BA_LOW (0x00249000)
|
||||
#define WCN3990_CE10_SR_BA_LOW (0x0024A000)
|
||||
#define WCN3990_CE11_SR_BA_LOW (0x0024B000)
|
||||
#define WCN3990_CE0_DR_BA_LOW (0x0024000C)
|
||||
#define WNC3990_CE0_DR_SIZE (0x00240014)
|
||||
#define WCN3990_CE0_CE_CTRL1 (0x00240018)
|
||||
#define WCN3990_CE0_HOST_IE (0x0024002C)
|
||||
#define WCN3990_CE0_HOST_IS (0x00240030)
|
||||
#define WCN3990_CE0_MISC_IE (0x00240034)
|
||||
#define WCN3990_CE0_MISC_IS (0x00240038)
|
||||
#define WCN3990_CE0_SRC_WR_INDEX (0x0024003C)
|
||||
#define WCN3990_CE0_CURRENT_SRRI (0x00240044)
|
||||
#define WCN3990_CE0_CURRENT_DRRI (0x00240048)
|
||||
#define WCN3990_CE0_SRC_WATERMARK (0x0024004C)
|
||||
#define WCN3990_CE0_DST_WATERMARK (0x00240050)
|
||||
#define WCN3990_CE0_SR_SIZE (0x00240008)
|
||||
#define HOST_IE_COPY_COMPLETE_MASK (0x00000001)
|
||||
#define WCN3990_CE_WRAPPER_HOST_INTERRUPT_SUMMARY 0x0024C000
|
||||
#define WCN3990_CE_WRAPPER_INDEX_BASE_LOW 0x0024C004
|
||||
#define WCN3990_CE_WRAPPER_INDEX_BASE_HIGH 0x0024C008
|
||||
#define CE_CTRL1_IDX_UPD_EN 0x00080000
|
||||
|
||||
#define WCN3990_CE_WRAPPER_BASE_ADDRESS \
|
||||
WCN3990_CE_WRAPPER_HOST_INTERRUPT_SUMMARY
|
||||
#define WCN3990_CE0_BASE_ADDRESS \
|
||||
WCN3990_CE0_SR_BA_LOW
|
||||
#define WCN3990_CE1_BASE_ADDRESS \
|
||||
WCN3990_CE1_SR_BA_LOW
|
||||
#define WCN3990_CE2_BASE_ADDRESS \
|
||||
WCN3990_CE2_SR_BA_LOW
|
||||
#define WCN3990_CE3_BASE_ADDRESS \
|
||||
WCN3990_CE3_SR_BA_LOW
|
||||
#define WCN3990_CE4_BASE_ADDRESS \
|
||||
WCN3990_CE4_SR_BA_LOW
|
||||
#define WCN3990_CE5_BASE_ADDRESS \
|
||||
WCN3990_CE5_SR_BA_LOW
|
||||
#define WCN3990_CE6_BASE_ADDRESS \
|
||||
WCN3990_CE6_SR_BA_LOW
|
||||
#define WCN3990_CE7_BASE_ADDRESS \
|
||||
WCN3990_CE7_SR_BA_LOW
|
||||
#define WCN3990_CE8_BASE_ADDRESS \
|
||||
WCN3990_CE8_SR_BA_LOW
|
||||
#define WCN3990_CE9_BASE_ADDRESS \
|
||||
WCN3990_CE9_SR_BA_LOW
|
||||
#define WCN3990_CE10_BASE_ADDRESS \
|
||||
WCN3990_CE10_SR_BA_LOW
|
||||
#define WCN3990_CE11_BASE_ADDRESS \
|
||||
WCN3990_CE11_SR_BA_LOW
|
||||
|
||||
#define SR_BA_ADDRESS (WCN3990_CE0_SR_BA_LOW\
|
||||
- WCN3990_CE0_BASE_ADDRESS)
|
||||
#define SR_SIZE_ADDRESS (WCN3990_CE0_SR_SIZE \
|
||||
- WCN3990_CE0_BASE_ADDRESS)
|
||||
#define DR_BA_ADDRESS (WCN3990_CE0_DR_BA_LOW\
|
||||
- WCN3990_CE0_BASE_ADDRESS)
|
||||
#define DR_SIZE_ADDRESS (WNC3990_CE0_DR_SIZE\
|
||||
- WCN3990_CE0_BASE_ADDRESS)
|
||||
#define WCN3990_CE_DDR_ADDRESS_FOR_RRI_LOW \
|
||||
(WCN3990_CE_WRAPPER_INDEX_BASE_LOW - WCN3990_CE_WRAPPER_BASE_ADDRESS)
|
||||
|
||||
#define WCN3990_CE_DDR_ADDRESS_FOR_RRI_HIGH \
|
||||
(WCN3990_CE_WRAPPER_INDEX_BASE_HIGH - WCN3990_CE_WRAPPER_BASE_ADDRESS)
|
||||
|
||||
#define CE_RRI_LOW (WCN3990_CE_WRAPPER_BASE_ADDRESS \
|
||||
+ WCN3990_CE_DDR_ADDRESS_FOR_RRI_LOW)
|
||||
|
||||
#define CE_RRI_HIGH (WCN3990_CE_WRAPPER_BASE_ADDRESS \
|
||||
+ WCN3990_CE_DDR_ADDRESS_FOR_RRI_HIGH)
|
||||
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB 18
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 18
|
||||
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00040000
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \
|
||||
(((0 | (x)) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
|
||||
CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
|
||||
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MSB 16
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
|
||||
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00020000
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_GET(x) \
|
||||
(((x) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) >> \
|
||||
CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \
|
||||
(((0 | (x)) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
|
||||
CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
|
||||
|
||||
#define CE_CTRL1_DMAX_LENGTH_MSB 0
|
||||
#define CE_CTRL1_DMAX_LENGTH_LSB 0
|
||||
|
||||
#define CE_CTRL1_DMAX_LENGTH_MASK 0x0000FFFF
|
||||
#define CE_CTRL1_DMAX_LENGTH_GET(x) \
|
||||
(((x) & CE_CTRL1_DMAX_LENGTH_MASK) >> CE_CTRL1_DMAX_LENGTH_LSB)
|
||||
#define CE_CTRL1_DMAX_LENGTH_SET(x) \
|
||||
(((0 | (x)) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
|
||||
|
||||
#define CE_CTRL1_ADDRESS (WCN3990_CE0_CE_CTRL1 \
|
||||
- WCN3990_CE0_BASE_ADDRESS)
|
||||
|
||||
#define HOST_IE_ADDRESS (WCN3990_CE0_HOST_IE\
|
||||
- WCN3990_CE0_BASE_ADDRESS)
|
||||
|
||||
#define HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
|
||||
#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008
|
||||
#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004
|
||||
#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002
|
||||
#define HOST_IS_COPY_COMPLETE_MASK 0x00000001
|
||||
#define HOST_IS_ADDRESS (WCN3990_CE0_HOST_IS \
|
||||
- WCN3990_CE0_BASE_ADDRESS)
|
||||
#define MISC_IE_ADDRESS (WCN3990_CE0_MISC_IE \
|
||||
- WCN3990_CE0_BASE_ADDRESS)
|
||||
|
||||
#define MISC_IS_AXI_ERR_MASK 0x00000100
|
||||
#define MISC_IS_DST_ADDR_ERR_MASK 0x00000200
|
||||
#define MISC_IS_SRC_LEN_ERR_MASK 0x00000100
|
||||
#define MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080
|
||||
#define MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040
|
||||
#define MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020
|
||||
#define MISC_IS_ADDRESS (WCN3990_CE0_MISC_IS \
|
||||
- WCN3990_CE0_BASE_ADDRESS)
|
||||
|
||||
#define SR_WR_INDEX_ADDRESS 0x3C
|
||||
#define DST_WR_INDEX_ADDRESS 0x40
|
||||
|
||||
#define CURRENT_SRRI_ADDRESS (WCN3990_CE0_CURRENT_SRRI\
|
||||
- WCN3990_CE0_BASE_ADDRESS)
|
||||
#define CURRENT_DRRI_ADDRESS (WCN3990_CE0_CURRENT_DRRI\
|
||||
- WCN3990_CE0_BASE_ADDRESS)
|
||||
|
||||
#define SRC_WATERMARK_LOW_MSB 0
|
||||
#define SRC_WATERMARK_LOW_LSB 16
|
||||
|
||||
#define SRC_WATERMARK_LOW_MASK 0xffff0000
|
||||
#define SRC_WATERMARK_LOW_GET(x) \
|
||||
(((x) & SRC_WATERMARK_LOW_MASK) >> SRC_WATERMARK_LOW_LSB)
|
||||
#define SRC_WATERMARK_LOW_SET(x) \
|
||||
(((0 | (x)) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
|
||||
|
||||
#define SRC_WATERMARK_LOW_RESET 0
|
||||
#define SRC_WATERMARK_HIGH_MSB 15
|
||||
#define SRC_WATERMARK_HIGH_LSB 0
|
||||
#define SRC_WATERMARK_HIGH_MASK 0x0000ffff
|
||||
#define SRC_WATERMARK_HIGH_GET(x) \
|
||||
(((x) & SRC_WATERMARK_HIGH_MASK) >> SRC_WATERMARK_HIGH_LSB)
|
||||
#define SRC_WATERMARK_HIGH_SET(x) \
|
||||
(((0 | (x)) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
|
||||
|
||||
#define SRC_WATERMARK_HIGH_RESET 0
|
||||
#define SRC_WATERMARK_ADDRESS (WCN3990_CE0_SRC_WATERMARK\
|
||||
- WCN3990_CE0_BASE_ADDRESS)
|
||||
|
||||
#define DST_WATERMARK_LOW_LSB 16
|
||||
#define DST_WATERMARK_LOW_MASK 0xffff0000
|
||||
#define DST_WATERMARK_LOW_SET(x) \
|
||||
(((0 | (x)) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
|
||||
#define DST_WATERMARK_LOW_RESET 0
|
||||
#define DST_WATERMARK_HIGH_MSB 15
|
||||
#define DST_WATERMARK_HIGH_LSB 0
|
||||
#define DST_WATERMARK_HIGH_MASK 0x0000ffff
|
||||
#define DST_WATERMARK_HIGH_GET(x) \
|
||||
(((x) & DST_WATERMARK_HIGH_MASK) >> DST_WATERMARK_HIGH_LSB)
|
||||
#define DST_WATERMARK_HIGH_SET(x) \
|
||||
(((0 | (x)) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
|
||||
#define DST_WATERMARK_HIGH_RESET 0
|
||||
#define DST_WATERMARK_ADDRESS (WCN3990_CE0_DST_WATERMARK \
|
||||
- WCN3990_CE0_BASE_ADDRESS)
|
||||
|
||||
#define BITS0_TO_31(val) ((uint32_t)((uint64_t)(val)\
|
||||
& (uint64_t)(0xFFFFFFFF)))
|
||||
#define BITS32_TO_35(val) ((uint32_t)(((uint64_t)(val)\
|
||||
& (uint64_t)(0xF00000000)) >> 32))
|
||||
#endif
|
||||
|
||||
#define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) ((COPY_ENGINE_BASE_ADDRESS \
|
||||
- CE0_BASE_ADDRESS) / (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS))
|
||||
|
||||
|
|
@ -675,18 +364,6 @@ static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
|
|||
return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
|
||||
}
|
||||
|
||||
#define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \
|
||||
HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \
|
||||
HOST_IS_DST_RING_LOW_WATERMARK_MASK | \
|
||||
HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
|
||||
|
||||
#define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \
|
||||
MISC_IS_DST_ADDR_ERR_MASK | \
|
||||
MISC_IS_SRC_LEN_ERR_MASK | \
|
||||
MISC_IS_DST_MAX_LEN_VIO_MASK | \
|
||||
MISC_IS_DST_RING_OVERFLOW_MASK | \
|
||||
MISC_IS_SRC_RING_OVERFLOW_MASK)
|
||||
|
||||
#define CE_SRC_RING_TO_DESC(baddr, idx) \
|
||||
(&(((struct ce_desc *)baddr)[idx]))
|
||||
|
||||
|
|
|
|||
|
|
@ -2324,28 +2324,34 @@ struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
|
|||
case ATH10K_HW_QCA988X:
|
||||
case ATH10K_HW_QCA9887:
|
||||
ar->regs = &qca988x_regs;
|
||||
ar->hw_ce_regs = &qcax_ce_regs;
|
||||
ar->hw_values = &qca988x_values;
|
||||
break;
|
||||
case ATH10K_HW_QCA6174:
|
||||
case ATH10K_HW_QCA9377:
|
||||
ar->regs = &qca6174_regs;
|
||||
ar->hw_ce_regs = &qcax_ce_regs;
|
||||
ar->hw_values = &qca6174_values;
|
||||
break;
|
||||
case ATH10K_HW_QCA99X0:
|
||||
case ATH10K_HW_QCA9984:
|
||||
ar->regs = &qca99x0_regs;
|
||||
ar->hw_ce_regs = &qcax_ce_regs;
|
||||
ar->hw_values = &qca99x0_values;
|
||||
break;
|
||||
case ATH10K_HW_QCA9888:
|
||||
ar->regs = &qca99x0_regs;
|
||||
ar->hw_ce_regs = &qcax_ce_regs;
|
||||
ar->hw_values = &qca9888_values;
|
||||
break;
|
||||
case ATH10K_HW_QCA4019:
|
||||
ar->regs = &qca4019_regs;
|
||||
ar->hw_ce_regs = &qcax_ce_regs;
|
||||
ar->hw_values = &qca4019_values;
|
||||
break;
|
||||
case ATH10K_HW_WCN3990:
|
||||
ar->regs = &wcn3990_regs;
|
||||
ar->hw_ce_regs = &wcn3990_ce_regs;
|
||||
ar->hw_values = &wcn3990_values;
|
||||
/* WCN3990 chip set is non bmi based */
|
||||
ar->is_bmi = false;
|
||||
|
|
|
|||
|
|
@ -740,6 +740,7 @@ struct ath10k {
|
|||
struct completion target_suspend;
|
||||
|
||||
const struct ath10k_hw_regs *regs;
|
||||
const struct ath10k_hw_ce_regs *hw_ce_regs;
|
||||
const struct ath10k_hw_values *hw_values;
|
||||
struct ath10k_shadow_reg_value *shadow_reg_value;
|
||||
struct ath10k_shadow_reg_address *shadow_reg_address;
|
||||
|
|
|
|||
|
|
@ -541,6 +541,7 @@ struct htt_rx_indication_hdr {
|
|||
#define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24
|
||||
|
||||
#define HTT_WCN3990_PADDR_MASK 0x1F
|
||||
#define HTT_WCN3990_ARCH_PADDR_MASK 0x1FFFFFFFFF
|
||||
|
||||
enum htt_rx_legacy_rate {
|
||||
HTT_RX_OFDM_48 = 0,
|
||||
|
|
@ -865,8 +866,7 @@ struct htt_rx_offload_ind {
|
|||
|
||||
struct htt_rx_in_ord_msdu_desc {
|
||||
#ifdef CONFIG_ATH10K_SNOC
|
||||
__le32 msdu_paddr_lo;
|
||||
__le32 msdu_paddr_hi;
|
||||
__le64 msdu_paddr;
|
||||
#else
|
||||
__le32 msdu_paddr;
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -429,9 +429,8 @@ static int ath10k_htt_rx_pop_paddr_list(struct ath10k_htt *htt,
|
|||
|
||||
while (msdu_count--) {
|
||||
#ifdef CONFIG_ATH10K_SNOC
|
||||
paddr = __le32_to_cpu(msdu_desc->msdu_paddr_lo);
|
||||
paddr |= ((u64)(msdu_desc->msdu_paddr_hi &
|
||||
HTT_WCN3990_PADDR_MASK) << 32);
|
||||
paddr = __le64_to_cpu(msdu_desc->msdu_paddr);
|
||||
paddr &= HTT_WCN3990_ARCH_PADDR_MASK;
|
||||
#else
|
||||
paddr = __le32_to_cpu(msdu_desc->msdu_paddr);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -164,6 +164,301 @@ const struct ath10k_hw_regs wcn3990_regs = {
|
|||
.pcie_intr_fw_mask = 0x00100000,
|
||||
};
|
||||
|
||||
static unsigned int
|
||||
ath10k_set_ring_byte(unsigned int offset,
|
||||
struct ath10k_hw_ce_regs_addr_map *addr_map)
|
||||
{
|
||||
return (((0 | (offset)) << addr_map->lsb) & addr_map->mask);
|
||||
}
|
||||
|
||||
static unsigned int
|
||||
ath10k_get_ring_byte(unsigned int offset,
|
||||
struct ath10k_hw_ce_regs_addr_map *addr_map)
|
||||
{
|
||||
return (((offset) & addr_map->mask) >> (addr_map->lsb));
|
||||
}
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map wcn3990_src_ring = {
|
||||
.msb = 0x00000010,
|
||||
.lsb = 0x00000010,
|
||||
.mask = 0x00020000,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
.get = &ath10k_get_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map wcn3990_dst_ring = {
|
||||
.msb = 0x00000012,
|
||||
.lsb = 0x00000012,
|
||||
.mask = 0x00040000,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
.get = &ath10k_get_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map wcn3990_dmax = {
|
||||
.msb = 0x00000000,
|
||||
.lsb = 0x00000000,
|
||||
.mask = 0x0000ffff,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
.get = &ath10k_get_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_ctrl1 wcn3990_ctrl1 = {
|
||||
.addr = 0x00000018,
|
||||
.src_ring = &wcn3990_src_ring,
|
||||
.dst_ring = &wcn3990_dst_ring,
|
||||
.dmax = &wcn3990_dmax,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map wcn3990_host_ie_cc = {
|
||||
.mask = 0x00000001,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_host_ie wcn3990_host_ie = {
|
||||
.copy_complete = &wcn3990_host_ie_cc,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_host_wm_regs wcn3990_wm_reg = {
|
||||
.dstr_lmask = 0x00000010,
|
||||
.dstr_hmask = 0x00000008,
|
||||
.srcr_lmask = 0x00000004,
|
||||
.srcr_hmask = 0x00000002,
|
||||
.cc_mask = 0x00000001,
|
||||
.wm_mask = 0x0000001E,
|
||||
.addr = 0x00000030,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_misc_regs wcn3990_misc_reg = {
|
||||
.axi_err = 0x00000100,
|
||||
.dstr_add_err = 0x00000200,
|
||||
.srcr_len_err = 0x00000100,
|
||||
.dstr_mlen_vio = 0x00000080,
|
||||
.dstr_overflow = 0x00000040,
|
||||
.srcr_overflow = 0x00000020,
|
||||
.err_mask = 0x000003E0,
|
||||
.addr = 0x00000038,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_low = {
|
||||
.msb = 0x00000000,
|
||||
.lsb = 0x00000010,
|
||||
.mask = 0xffff0000,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
.get = &ath10k_get_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map wcn3990_src_wm_high = {
|
||||
.msb = 0x0000000f,
|
||||
.lsb = 0x00000000,
|
||||
.mask = 0x0000ffff,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
.get = &ath10k_get_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_src_ring = {
|
||||
.addr = 0x0000004c,
|
||||
.low_rst = 0x00000000,
|
||||
.high_rst = 0x00000000,
|
||||
.wm_low = &wcn3990_src_wm_low,
|
||||
.wm_high = &wcn3990_src_wm_high,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_low = {
|
||||
.lsb = 0x00000010,
|
||||
.mask = 0xffff0000,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map wcn3990_dst_wm_high = {
|
||||
.msb = 0x0000000f,
|
||||
.lsb = 0x00000000,
|
||||
.mask = 0x0000ffff,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
.get = &ath10k_get_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_dst_src_wm_regs wcn3990_wm_dst_ring = {
|
||||
.addr = 0x00000050,
|
||||
.low_rst = 0x00000000,
|
||||
.high_rst = 0x00000000,
|
||||
.wm_low = &wcn3990_dst_wm_low,
|
||||
.wm_high = &wcn3990_dst_wm_high,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs wcn3990_ce_regs = {
|
||||
.sr_base_addr = 0x00000000,
|
||||
.sr_size_addr = 0x00000008,
|
||||
.dr_base_addr = 0x0000000c,
|
||||
.dr_size_addr = 0x00000014,
|
||||
.misc_ie_addr = 0x00000034,
|
||||
.sr_wr_index_addr = 0x0000003c,
|
||||
.dst_wr_index_addr = 0x00000040,
|
||||
.current_srri_addr = 0x00000044,
|
||||
.current_drri_addr = 0x00000048,
|
||||
.ddr_addr_for_rri_low = 0x00000004,
|
||||
.ddr_addr_for_rri_high = 0x00000008,
|
||||
.ce_rri_low = 0x0024C004,
|
||||
.ce_rri_high = 0x0024C008,
|
||||
.host_ie_addr = 0x0000002c,
|
||||
.ctrl1_regs = &wcn3990_ctrl1,
|
||||
.host_ie = &wcn3990_host_ie,
|
||||
.wm_regs = &wcn3990_wm_reg,
|
||||
.misc_regs = &wcn3990_misc_reg,
|
||||
.wm_srcr = &wcn3990_wm_src_ring,
|
||||
.wm_dstr = &wcn3990_wm_dst_ring,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map qcax_src_ring = {
|
||||
.msb = 0x00000010,
|
||||
.lsb = 0x00000010,
|
||||
.mask = 0x00010000,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map qcax_dst_ring = {
|
||||
.msb = 0x00000011,
|
||||
.lsb = 0x00000011,
|
||||
.mask = 0x00020000,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
.get = &ath10k_get_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map qcax_dmax = {
|
||||
.msb = 0x0000000f,
|
||||
.lsb = 0x00000000,
|
||||
.mask = 0x0000ffff,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
.get = &ath10k_get_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_ctrl1 qcax_ctrl1 = {
|
||||
.addr = 0x00000010,
|
||||
.hw_mask = 0x0007ffff,
|
||||
.sw_mask = 0x0007ffff,
|
||||
.hw_wr_mask = 0x00000000,
|
||||
.sw_wr_mask = 0x0007ffff,
|
||||
.reset_mask = 0xffffffff,
|
||||
.reset = 0x00000080,
|
||||
.src_ring = &qcax_src_ring,
|
||||
.dst_ring = &qcax_dst_ring,
|
||||
.dmax = &qcax_dmax,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map qcax_cmd_halt_status = {
|
||||
.msb = 0x00000003,
|
||||
.lsb = 0x00000003,
|
||||
.mask = 0x00000008,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
.get = &ath10k_get_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_cmd_halt qcax_cmd_halt = {
|
||||
.msb = 0x00000000,
|
||||
.mask = 0x00000001,
|
||||
.status_reset = 0x00000000,
|
||||
.status = &qcax_cmd_halt_status,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map qcax_host_ie_cc = {
|
||||
.msb = 0x00000000,
|
||||
.lsb = 0x00000000,
|
||||
.mask = 0x00000001,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
.get = &ath10k_get_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_host_ie qcax_host_ie = {
|
||||
.copy_complete_reset = 0x00000000,
|
||||
.copy_complete = &qcax_host_ie_cc,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_host_wm_regs qcax_wm_reg = {
|
||||
.dstr_lmask = 0x00000010,
|
||||
.dstr_hmask = 0x00000008,
|
||||
.srcr_lmask = 0x00000004,
|
||||
.srcr_hmask = 0x00000002,
|
||||
.cc_mask = 0x00000001,
|
||||
.wm_mask = 0x0000001E,
|
||||
.addr = 0x00000030,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_misc_regs qcax_misc_reg = {
|
||||
.axi_err = 0x00000400,
|
||||
.dstr_add_err = 0x00000200,
|
||||
.srcr_len_err = 0x00000100,
|
||||
.dstr_mlen_vio = 0x00000080,
|
||||
.dstr_overflow = 0x00000040,
|
||||
.srcr_overflow = 0x00000020,
|
||||
.err_mask = 0x000007E0,
|
||||
.addr = 0x00000038,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map qcax_src_wm_low = {
|
||||
.msb = 0x0000001f,
|
||||
.lsb = 0x00000010,
|
||||
.mask = 0xffff0000,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
.get = &ath10k_get_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map qcax_src_wm_high = {
|
||||
.msb = 0x0000000f,
|
||||
.lsb = 0x00000000,
|
||||
.mask = 0x0000ffff,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
.get = &ath10k_get_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_src_ring = {
|
||||
.addr = 0x0000004c,
|
||||
.low_rst = 0x00000000,
|
||||
.high_rst = 0x00000000,
|
||||
.wm_low = &qcax_src_wm_low,
|
||||
.wm_high = &qcax_src_wm_high,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_low = {
|
||||
.lsb = 0x00000010,
|
||||
.mask = 0xffff0000,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map qcax_dst_wm_high = {
|
||||
.msb = 0x0000000f,
|
||||
.lsb = 0x00000000,
|
||||
.mask = 0x0000ffff,
|
||||
.set = &ath10k_set_ring_byte,
|
||||
.get = &ath10k_get_ring_byte,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_dst_src_wm_regs qcax_wm_dst_ring = {
|
||||
.addr = 0x00000050,
|
||||
.low_rst = 0x00000000,
|
||||
.high_rst = 0x00000000,
|
||||
.wm_low = &qcax_dst_wm_low,
|
||||
.wm_high = &qcax_dst_wm_high,
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs qcax_ce_regs = {
|
||||
.sr_base_addr = 0x00000000,
|
||||
.sr_size_addr = 0x00000004,
|
||||
.dr_base_addr = 0x00000008,
|
||||
.dr_size_addr = 0x0000000c,
|
||||
.ce_cmd_addr = 0x00000018,
|
||||
.misc_ie_addr = 0x00000034,
|
||||
.sr_wr_index_addr = 0x0000003c,
|
||||
.dst_wr_index_addr = 0x00000040,
|
||||
.current_srri_addr = 0x00000044,
|
||||
.current_drri_addr = 0x00000048,
|
||||
.host_ie_addr = 0x0000002c,
|
||||
.ctrl1_regs = &qcax_ctrl1,
|
||||
.cmd_halt = &qcax_cmd_halt,
|
||||
.host_ie = &qcax_host_ie,
|
||||
.wm_regs = &qcax_wm_reg,
|
||||
.misc_regs = &qcax_misc_reg,
|
||||
.wm_srcr = &qcax_wm_src_ring,
|
||||
.wm_dstr = &qcax_wm_dst_ring,
|
||||
};
|
||||
|
||||
const struct ath10k_hw_values qca988x_values = {
|
||||
.rtc_state_val_on = 3,
|
||||
.ce_count = 8,
|
||||
|
|
|
|||
|
|
@ -268,6 +268,98 @@ extern const struct ath10k_hw_regs qca99x0_regs;
|
|||
extern const struct ath10k_hw_regs qca4019_regs;
|
||||
extern const struct ath10k_hw_regs wcn3990_regs;
|
||||
|
||||
struct ath10k_hw_ce_regs_addr_map {
|
||||
u32 msb;
|
||||
u32 lsb;
|
||||
u32 mask;
|
||||
unsigned int (*set)(unsigned int offset,
|
||||
struct ath10k_hw_ce_regs_addr_map *addr_map);
|
||||
unsigned int (*get)(unsigned int offset,
|
||||
struct ath10k_hw_ce_regs_addr_map *addr_map);
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_ctrl1 {
|
||||
u32 addr;
|
||||
u32 hw_mask;
|
||||
u32 sw_mask;
|
||||
u32 hw_wr_mask;
|
||||
u32 sw_wr_mask;
|
||||
u32 reset_mask;
|
||||
u32 reset;
|
||||
struct ath10k_hw_ce_regs_addr_map *src_ring;
|
||||
struct ath10k_hw_ce_regs_addr_map *dst_ring;
|
||||
struct ath10k_hw_ce_regs_addr_map *dmax;
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_cmd_halt {
|
||||
u32 status_reset;
|
||||
u32 msb;
|
||||
u32 mask;
|
||||
struct ath10k_hw_ce_regs_addr_map *status;
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_host_ie {
|
||||
u32 copy_complete_reset;
|
||||
struct ath10k_hw_ce_regs_addr_map *copy_complete;
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_host_wm_regs {
|
||||
u32 dstr_lmask;
|
||||
u32 dstr_hmask;
|
||||
u32 srcr_lmask;
|
||||
u32 srcr_hmask;
|
||||
u32 cc_mask;
|
||||
u32 wm_mask;
|
||||
u32 addr;
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_misc_regs {
|
||||
u32 axi_err;
|
||||
u32 dstr_add_err;
|
||||
u32 srcr_len_err;
|
||||
u32 dstr_mlen_vio;
|
||||
u32 dstr_overflow;
|
||||
u32 srcr_overflow;
|
||||
u32 err_mask;
|
||||
u32 addr;
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_dst_src_wm_regs {
|
||||
u32 addr;
|
||||
u32 low_rst;
|
||||
u32 high_rst;
|
||||
struct ath10k_hw_ce_regs_addr_map *wm_low;
|
||||
struct ath10k_hw_ce_regs_addr_map *wm_high;
|
||||
};
|
||||
|
||||
struct ath10k_hw_ce_regs {
|
||||
u32 sr_base_addr;
|
||||
u32 sr_size_addr;
|
||||
u32 dr_base_addr;
|
||||
u32 dr_size_addr;
|
||||
u32 ce_cmd_addr;
|
||||
u32 misc_ie_addr;
|
||||
u32 sr_wr_index_addr;
|
||||
u32 dst_wr_index_addr;
|
||||
u32 current_srri_addr;
|
||||
u32 current_drri_addr;
|
||||
u32 ddr_addr_for_rri_low;
|
||||
u32 ddr_addr_for_rri_high;
|
||||
u32 ce_rri_low;
|
||||
u32 ce_rri_high;
|
||||
u32 host_ie_addr;
|
||||
struct ath10k_hw_ce_host_wm_regs *wm_regs;
|
||||
struct ath10k_hw_ce_misc_regs *misc_regs;
|
||||
struct ath10k_hw_ce_ctrl1 *ctrl1_regs;
|
||||
struct ath10k_hw_ce_cmd_halt *cmd_halt;
|
||||
struct ath10k_hw_ce_host_ie *host_ie;
|
||||
struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr;
|
||||
struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr;
|
||||
};
|
||||
|
||||
extern struct ath10k_hw_ce_regs wcn3990_ce_regs;
|
||||
extern struct ath10k_hw_ce_regs qcax_ce_regs;
|
||||
|
||||
extern struct fw_flag wcn3990_fw_flags;
|
||||
|
||||
struct ath10k_hw_values {
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue