msm: kgsl: Leave the MMU clocks on with the rest of the GPU

It is no longer power efficient to independently enable and disable
the MMU clocks. We can safely enable and disable them with the rest
of the GPU clocks and take back the infrastructure needed to handle
the clocks.

CRs-Fixed: 1009124
Change-Id: Ic0dedbadc48095eada9c5fce6004475a2cb0f0a9
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>

drivers/gpu/msm/adreno_a4xx.c

@@ -2034,8 +2034,6 @@ static void a4xx_preempt_clear_state(
 {
 	struct adreno_dispatcher *dispatcher = &adreno_dev->dispatcher;
 	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
-	struct adreno_dispatcher_cmdqueue *dispatch_tempq;
-	struct kgsl_cmdbatch *cmdbatch;
 	struct adreno_ringbuffer *highest_busy_rb;
 	int switch_low_to_high;
 	int ret;
@@ -2089,9 +2087,6 @@ static void a4xx_preempt_clear_state(
 	 */
 	a4xx_preemption_start(adreno_dev, highest_busy_rb);
 
-	/* turn on IOMMU as the preemption may trigger pt switch */
-	kgsl_mmu_enable_clk(&device->mmu);
-
 	atomic_set(&dispatcher->preemption_state,
 			ADRENO_DISPATCHER_PREEMPT_TRIGGERED);
 
@@ -2105,22 +2100,7 @@ static void a4xx_preempt_clear_state(
 			adreno_get_rptr(adreno_dev->next_rb));
 	/* issue PREEMPT trigger */
 	adreno_writereg(adreno_dev, ADRENO_REG_CP_PREEMPT, 1);
-	/*
+
-	 * IOMMU clock can be safely switched off after the timestamp
-	 * of the first command in the new rb
-	 */
-	dispatch_tempq = &adreno_dev->next_rb->dispatch_q;
-	if (dispatch_tempq->head != dispatch_tempq->tail)
-		cmdbatch = dispatch_tempq->cmd_q[dispatch_tempq->head];
-	else
-		cmdbatch = NULL;
-	if (cmdbatch)
-		adreno_ringbuffer_mmu_disable_clk_on_ts(device,
-			adreno_dev->next_rb,
-			cmdbatch->global_ts);
-	else
-		adreno_ringbuffer_mmu_disable_clk_on_ts(device,
-			adreno_dev->next_rb, adreno_dev->next_rb->timestamp);
 	/* submit preempt token packet to ensure preemption */
 	if (switch_low_to_high < 0) {
 		ret = a4xx_submit_preempt_token(

drivers/gpu/msm/adreno_a4xx_snapshot.c

@@ -534,9 +534,6 @@ void a4xx_snapshot(struct adreno_device *adreno_dev,
 	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL, 0);
 	kgsl_regwrite(device, A4XX_RBBM_CLOCK_CTL2, 0);
 
-	/* Turn on MMU clocks since we read MMU registers */
-	kgsl_mmu_enable_clk(&device->mmu);
-
 	/* Master set of (non debug) registers */
 
 	SNAPSHOT_REGISTERS(device, snapshot, a4xx_registers);
@@ -554,8 +551,6 @@ void a4xx_snapshot(struct adreno_device *adreno_dev,
 		a4xx_vbif_snapshot_registers,
 		ARRAY_SIZE(a4xx_vbif_snapshot_registers));
 
-	kgsl_mmu_disable_clk(&device->mmu);
-
 	kgsl_snapshot_indexed_registers(device, snapshot,
 		A4XX_CP_STATE_DEBUG_INDEX, A4XX_CP_STATE_DEBUG_DATA,
 		0, snap_data->sect_sizes->cp_pfp);

drivers/gpu/msm/adreno_a5xx.c

@@ -3914,9 +3914,6 @@ static void a5xx_preempt_clear_state(
 			return;
 	}
 
-	/* turn on IOMMU as the preemption may trigger pt switch */
-	kgsl_mmu_enable_clk(&device->mmu);
-
 	/*
 	 * setup memory to do the switch to highest priority RB
 	 * which is not empty or may be starving away(poor thing)
@@ -4027,8 +4024,6 @@ static void a5xx_preempt_complete_state(
 				ADRENO_DISPATCHER_RB_STARVE_TIMER_UNINIT;
 		}
 	}
-	adreno_ringbuffer_mmu_disable_clk_on_ts(device, adreno_dev->cur_rb,
-						adreno_dev->cur_rb->timestamp);
 
 	atomic_set(&dispatcher->preemption_state,
 		ADRENO_DISPATCHER_PREEMPT_CLEAR);

drivers/gpu/msm/adreno_iommu.c

@@ -796,8 +796,6 @@ static int _set_pagetable_gpu(struct adreno_ringbuffer *rb,
 		return 0;
 	}
 
-	kgsl_mmu_enable_clk(KGSL_MMU(adreno_dev));
-
 	cmds += adreno_iommu_set_pt_generate_cmds(rb, cmds, new_pt);
 
 	if ((unsigned int) (cmds - link) > (PAGE_SIZE / sizeof(unsigned int))) {
@@ -813,16 +811,6 @@ static int _set_pagetable_gpu(struct adreno_ringbuffer *rb,
 			KGSL_CMD_FLAGS_PMODE, link,
 			(unsigned int)(cmds - link));
 
-	/*
-	 * On error disable the IOMMU clock right away otherwise turn it off
-	 * after the command has been retired
-	 */
-	if (result)
-		kgsl_mmu_disable_clk(KGSL_MMU(adreno_dev));
-	else
-		adreno_ringbuffer_mmu_disable_clk_on_ts(KGSL_DEVICE(adreno_dev),
-			rb, rb->timestamp);
-
 	kfree(link);
 	return result;
 }

drivers/gpu/msm/adreno_ringbuffer.c

@@ -1134,44 +1134,6 @@ done:
 	return ret;
 }
 
-/**
- * adreno_ringbuffer_mmu_clk_disable_event() - Callback function that
- * disables the MMU clocks.
- * @device: Device pointer
- * @context: The ringbuffer context pointer
- * @data: Pointer containing the adreno_mmu_disable_clk_param structure
- * @type: The event call type (RETIRED or CANCELLED)
- */
-static void adreno_ringbuffer_mmu_clk_disable_event(struct kgsl_device *device,
-			struct kgsl_event_group *group, void *data, int type)
-{
-	kgsl_mmu_disable_clk(&device->mmu);
-}
-
-/*
- * adreno_ringbuffer_mmu_disable_clk_on_ts() - Sets up event to disable MMU
- * clocks
- * @device - The kgsl device pointer
- * @rb: The ringbuffer in whose event list the event is added
- * @timestamp: The timestamp on which the event should trigger
- *
- * Creates an event to disable the MMU clocks on timestamp and if event
- * already exists then updates the timestamp of disabling the MMU clocks
- * with the passed in ts if it is greater than the current value at which
- * the clocks will be disabled
- * Return - void
- */
-void
-adreno_ringbuffer_mmu_disable_clk_on_ts(struct kgsl_device *device,
-			struct adreno_ringbuffer *rb, unsigned int timestamp)
-{
-	if (kgsl_add_event(device, &(rb->events), timestamp,
-		adreno_ringbuffer_mmu_clk_disable_event, NULL)) {
-		KGSL_DRV_ERR(device,
-			"Failed to add IOMMU disable clk event\n");
-	}
-}
-
 /**
  * adreno_ringbuffer_wait_callback() - Callback function for event registered
  * on a ringbuffer timestamp

drivers/gpu/msm/adreno_ringbuffer.h

@@ -165,9 +165,6 @@ void adreno_ringbuffer_read_pfp_ucode(struct kgsl_device *device);
 
 void adreno_ringbuffer_read_pm4_ucode(struct kgsl_device *device);
 
-void adreno_ringbuffer_mmu_disable_clk_on_ts(struct kgsl_device *device,
-			struct adreno_ringbuffer *rb, unsigned int ts);
-
 int adreno_ringbuffer_waittimestamp(struct adreno_ringbuffer *rb,
 					unsigned int timestamp,
 					unsigned int msecs);

drivers/gpu/msm/kgsl_pwrctrl.c

@@ -1381,6 +1381,9 @@ static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state,
 				_isense_clk_set_rate(pwr,
 					pwr->num_pwrlevels - 1);
 			}
+
+			/* Turn off the IOMMU clocks */
+			kgsl_mmu_disable_clk(&device->mmu);
 		} else if (requested_state == KGSL_STATE_SLEEP) {
 			/* High latency clock maintenance. */
 			for (i = KGSL_MAX_CLKS - 1; i > 0; i--)
@@ -1428,7 +1431,11 @@ static void kgsl_pwrctrl_clk(struct kgsl_device *device, int state,
 					pwr->gpu_bimc_interface_enabled = 1;
 				}
 			}
+
+			/* Turn on the IOMMU clocks */
+			kgsl_mmu_enable_clk(&device->mmu);
 		}
+
 	}
 }