msm: mdss: Add support for separate irq line for DSI 6G

In ferrum DSI has an irq line which is different from mdp.
Add support for irq handling this case. It makes use of
utility functions provided by mdss.

Change-Id: Ia6dca1050957f4755b7547f4c1a08ace913c2ac7
Signed-off-by: Shivaraj Shetty <shivaraj@codeaurora.org>
[cip@codeaurora.org: Resolved merge conflict,
removed IRQF_DISABLED flag]
Signed-off-by: Clarence Ip <cip@codeaurora.org>

Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt

@@ -74,6 +74,7 @@ Optional properties:
 - qcom,dsi-panel-bias-vreg:		Boolean to enable control of panel bias regulator
 - qcom,mmss-ulp-clamp-ctrl-offset:	Specifies the offset for dsi ulps clamp control register.
 - qcom,mmss-phyreset-ctrl-offset:	Specifies the offset for dsi phy reset control register.
+- qcom,dsi-irq-line:			Boolean specifies if DSI has a different irq line than mdp.
 
 Example:
         mdss_dsi0: qcom,mdss_dsi@fd922800 {
@@ -111,6 +112,7 @@ Example:
 		qcom,platform-bklight-en-gpio = <&msmgpio 86 0>;
 		qcom,platform-mode-gpio = <&msmgpio 7 0>;
 		qcom,dsi-panel-bias-vreg;
+		qcom,dsi-irq-line;
 
 		qcom,core-supply-entries {
 			#address-cells = <1>;

drivers/video/fbdev/msm/mdss.h

@@ -125,10 +125,6 @@ struct mdss_data_type {
 
 	struct mutex reg_lock;
 
-	u32 irq;
-	u32 irq_mask;
-	u32 irq_ena;
-	u32 irq_buzy;
 	u32 has_bwc;
 	u32 has_decimation;
 	bool has_fixed_qos_arbiter_enabled;
@@ -252,12 +248,21 @@ struct mdss_data_type {
 };
 extern struct mdss_data_type *mdss_res;
 
+struct irq_info {
+	u32 irq;
+	u32 irq_mask;
+	u32 irq_ena;
+	u32 irq_buzy;
+};
+
 struct mdss_hw {
 	u32 hw_ndx;
 	void *ptr;
+	struct irq_info *irq_info;
 	irqreturn_t (*irq_handler)(int irq, void *ptr);
 };
 
+struct irq_info *mdss_intr_line(void);
 void mdss_bus_bandwidth_ctrl(int enable);
 int mdss_iommu_ctrl(int enable);
 int mdss_bus_scale_set_quota(int client, u64 ab_quota_rt, u64 ab_quota_nrt,

drivers/video/fbdev/msm/mdss_dsi.c

@@ -1476,6 +1476,29 @@ int mdss_dsi_retrieve_ctrl_resources(struct platform_device *pdev, int mode,
 	return 0;
 }
 
+static int mdss_dsi_irq_init(struct device *dev, int irq_no,
+			struct mdss_dsi_ctrl_pdata *ctrl)
+{
+	int ret;
+
+	ret = devm_request_irq(dev, irq_no, mdss_dsi_isr,
+				0x0, "DSI", ctrl);
+	if (ret) {
+		pr_err("msm_dsi_irq_init request_irq() failed!\n");
+	} else {
+		ctrl->dsi_hw->irq_info =
+			kzalloc(sizeof(struct irq_info), GFP_KERNEL);
+		if (!ctrl->dsi_hw->irq_info) {
+			pr_err("no mem to save irq info: kzalloc fail\n");
+			return -ENOMEM;
+		}
+		ctrl->dsi_hw->irq_info->irq = irq_no;
+		ctrl->dsi_hw->irq_info->irq_ena = false;
+	}
+
+	return ret;
+}
+
 int dsi_panel_device_register(struct device_node *pan_node,
 				struct mdss_dsi_ctrl_pdata *ctrl_pdata)
 {
@@ -1485,6 +1508,7 @@ int dsi_panel_device_register(struct device_node *pan_node,
 	struct device_node *dsi_ctrl_np = NULL;
 	struct platform_device *ctrl_pdev = NULL;
 	const char *data;
+	struct resource *res;
 
 	mipi  = &(pinfo->mipi);
 
@@ -1631,6 +1655,26 @@ int dsi_panel_device_register(struct device_node *pan_node,
 		return -EPERM;
 	}
 
+	ctrl_pdata->dsi_irq_line = of_property_read_bool(
+				ctrl_pdev->dev.of_node, "qcom,dsi-irq-line");
+
+	if (ctrl_pdata->dsi_irq_line) {
+		/* DSI has it's own irq line */
+		res = platform_get_resource(ctrl_pdev, IORESOURCE_IRQ, 0);
+		if (!res || res->start == 0) {
+			pr_err("%s:%d unable to get the MDSS irq resources\n",
+							__func__, __LINE__);
+			rc = -ENODEV;
+		}
+		rc = mdss_dsi_irq_init(&ctrl_pdev->dev, res->start,
+						   ctrl_pdata);
+		if (rc) {
+			dev_err(&ctrl_pdev->dev, "%s: failed to init irq\n",
+							__func__);
+			return rc;
+		}
+	}
+
 	ctrl_pdata->panel_data.event_handler = mdss_dsi_event_handler;
 
 	if (ctrl_pdata->status_mode == ESD_REG ||

drivers/video/fbdev/msm/mdss_dsi.h

@@ -53,7 +53,6 @@
 #define MDSS_DSI_HW_REV_103		0x10030000	/* 8994    */
 #define MDSS_DSI_HW_REV_103_1		0x10030001	/* 8916/8936 */
 
-
 enum {		/* mipi dsi panel */
 	DSI_VIDEO_MODE,
 	DSI_CMD_MODE,
@@ -309,6 +308,7 @@ struct mdss_dsi_ctrl_pdata {
 	int new_fps;
 	int pwm_enabled;
 	bool panel_bias_vreg;
+	bool dsi_irq_line;
 
 	bool cmd_sync_wait_broadcast;
 	bool cmd_sync_wait_trigger;

drivers/video/fbdev/msm/mdss_dsi_host.c

@@ -81,6 +81,9 @@ void mdss_dsi_ctrl_init(struct device *ctrl_dev,
 		ctrl->ndx = DSI_CTRL_1;
 	}
 
+	if (!(ctrl->dsi_irq_line))
+		ctrl->dsi_hw->irq_info = mdss_intr_line();
+
 	ctrl->panel_mode = ctrl->panel_data.panel_info.mipi.mode;
 
 	ctrl_list[ctrl->ndx] = ctrl;	/* keep it */

drivers/video/fbdev/msm/mdss_edp.c

@@ -1122,6 +1122,12 @@ static int mdss_edp_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
+	mdss_edp_hw.irq_info = mdss_intr_line();
+	if (mdss_edp_hw.irq_info == NULL) {
+		pr_err("Failed to get mdss irq information\n");
+		return -ENODEV;
+	}
+
 	edp_drv->pdev = pdev;
 	edp_drv->pdev->id = 1;
 	edp_drv->clk_on = 0;

drivers/video/fbdev/msm/mdss_hdmi_tx.c

@@ -4028,6 +4028,12 @@ static int hdmi_tx_probe(struct platform_device *pdev)
 		goto failed_res_init;
 	}
 
+	hdmi_tx_hw.irq_info = mdss_intr_line();
+	if (hdmi_tx_hw.irq_info == NULL) {
+		pr_err("Failed to get mdss irq information\n");
+		return -ENODEV;
+	}
+
 	rc = hdmi_tx_init_resource(hdmi_ctrl);
 	if (rc) {
 		DEV_ERR("%s: FAILED: resource init. rc=%d\n",

drivers/video/fbdev/msm/mdss_mdp.c

@@ -234,7 +234,7 @@ static irqreturn_t mdss_irq_handler(int irq, void *ptr)
 	if (!mdata)
 		return IRQ_NONE;
 
-	mdata->irq_buzy = true;
+	mdss_mdp_hw.irq_info->irq_buzy = true;
 
 	if (intr & MDSS_INTR_MDP) {
 		spin_lock(&mdp_lock);
@@ -254,7 +254,7 @@ static irqreturn_t mdss_irq_handler(int irq, void *ptr)
 	if (intr & MDSS_INTR_HDMI)
 		mdata->mdss_util->irq_dispatch(MDSS_HW_HDMI, irq, ptr);
 
-	mdata->irq_buzy = false;
+	mdss_mdp_hw.irq_info->irq_buzy = false;
 
 	return IRQ_HANDLED;
 }
@@ -819,13 +819,13 @@ static int mdss_mdp_irq_clk_setup(struct mdss_data_type *mdata)
 
 	pr_debug("max mdp clk rate=%d\n", mdata->max_mdp_clk_rate);
 
-	ret = devm_request_irq(&mdata->pdev->dev, mdata->irq, mdss_irq_handler,
-			 0x0, "MDSS", mdata);
+	ret = devm_request_irq(&mdata->pdev->dev, mdss_mdp_hw.irq_info->irq,
+				mdss_irq_handler, 0x0, "MDSS", mdata);
 	if (ret) {
 		pr_err("mdp request_irq() failed!\n");
 		return ret;
 	}
-	disable_irq(mdata->irq);
+	disable_irq(mdss_mdp_hw.irq_info->irq);
 
 	mdata->fs = devm_regulator_get(&mdata->pdev->dev, "vdd");
 	if (IS_ERR_OR_NULL(mdata->fs)) {
@@ -1104,8 +1104,8 @@ static u32 mdss_mdp_res_init(struct mdss_data_type *mdata)
 
 	mdata->res_init = true;
 	mdata->clk_ena = false;
-	mdata->irq_mask = MDSS_MDP_DEFAULT_INTR_MASK;
-	mdata->irq_ena = false;
+	mdss_mdp_hw.irq_info->irq_mask = MDSS_MDP_DEFAULT_INTR_MASK;
+	mdss_mdp_hw.irq_info->irq_ena = false;
 
 	rc = mdss_mdp_irq_clk_setup(mdata);
 	if (rc)
@@ -1420,7 +1420,13 @@ static int mdss_mdp_probe(struct platform_device *pdev)
 		rc = -ENOMEM;
 		goto probe_done;
 	}
-	mdata->irq = res->start;
+
+	mdss_mdp_hw.irq_info = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
+	if (!mdss_mdp_hw.irq_info) {
+		pr_err("no mem to save irq info: kzalloc fail\n");
+		return -ENOMEM;
+	}
+	mdss_mdp_hw.irq_info->irq = res->start;
 	mdss_mdp_hw.ptr = mdata;
 
 	/*populate hw iomem base info from device tree*/
@@ -2790,6 +2796,12 @@ struct mdss_panel_cfg *mdss_panel_intf_type(int intf_val)
 }
 EXPORT_SYMBOL(mdss_panel_intf_type);
 
+struct irq_info *mdss_intr_line()
+{
+	return mdss_mdp_hw.irq_info;
+}
+EXPORT_SYMBOL(mdss_intr_line);
+
 int mdss_panel_get_boot_cfg(void)
 {
 	int rc;

drivers/video/fbdev/msm/mdss_util.c

@@ -56,17 +56,17 @@ void mdss_enable_irq(struct mdss_hw *hw)
 	ndx_bit = BIT(hw->hw_ndx);
 
 	pr_debug("Enable HW=%d irq ena=%d mask=%x\n", hw->hw_ndx,
-			mdss_res->irq_ena, mdss_res->irq_mask);
+			hw->irq_info->irq_ena, hw->irq_info->irq_mask);
 
 	spin_lock_irqsave(&mdss_lock, irq_flags);
-	if (mdss_res->irq_mask & ndx_bit) {
+	if (hw->irq_info->irq_mask & ndx_bit) {
 		pr_debug("MDSS HW ndx=%d is already set, mask=%x\n",
-				hw->hw_ndx, mdss_res->irq_mask);
+				hw->hw_ndx, hw->irq_info->irq_mask);
 	} else {
-		mdss_res->irq_mask |= ndx_bit;
-		if (!mdss_res->irq_ena) {
-			mdss_res->irq_ena = true;
-			enable_irq(mdss_res->irq);
+		hw->irq_info->irq_mask |= ndx_bit;
+		if (!hw->irq_info->irq_ena) {
+			hw->irq_info->irq_ena = true;
+			enable_irq(hw->irq_info->irq);
 		}
 	}
 	spin_unlock_irqrestore(&mdss_lock, irq_flags);
@@ -83,18 +83,16 @@ void mdss_disable_irq(struct mdss_hw *hw)
 	ndx_bit = BIT(hw->hw_ndx);
 
 	pr_debug("Disable HW=%d irq ena=%d mask=%x\n", hw->hw_ndx,
-			mdss_res->irq_ena, mdss_res->irq_mask);
+			hw->irq_info->irq_ena, hw->irq_info->irq_mask);
 
 	spin_lock_irqsave(&mdss_lock, irq_flags);
-	if (!(mdss_res->irq_mask & ndx_bit)) {
-		pr_warn("MDSS HW ndx=%d is NOT set, mask=%x, hist mask=%x\n",
-			hw->hw_ndx, mdss_res->mdp_irq_mask,
-			mdss_res->mdp_hist_irq_mask);
+	if (!(hw->irq_info->irq_mask & ndx_bit)) {
+		pr_warn("MDSS HW ndx=%d is NOT set\n", hw->hw_ndx);
 	} else {
-		mdss_res->irq_mask &= ~ndx_bit;
-		if (mdss_res->irq_mask == 0) {
-			mdss_res->irq_ena = false;
-			disable_irq_nosync(mdss_res->irq);
+		hw->irq_info->irq_mask &= ~ndx_bit;
+		if (hw->irq_info->irq_mask == 0) {
+			hw->irq_info->irq_ena = false;
+			disable_irq_nosync(hw->irq_info->irq);
 		}
 	}
 	spin_unlock_irqrestore(&mdss_lock, irq_flags);
@@ -111,18 +109,16 @@ void mdss_disable_irq_nosync(struct mdss_hw *hw)
 	ndx_bit = BIT(hw->hw_ndx);
 
 	pr_debug("Disable HW=%d irq ena=%d mask=%x\n", hw->hw_ndx,
-			mdss_res->irq_ena, mdss_res->irq_mask);
+			hw->irq_info->irq_ena, hw->irq_info->irq_mask);
 
 	spin_lock(&mdss_lock);
-	if (!(mdss_res->irq_mask & ndx_bit)) {
-		pr_warn("MDSS HW ndx=%d is NOT set, mask=%x, hist mask=%x\n",
-			hw->hw_ndx, mdss_res->mdp_irq_mask,
-			mdss_res->mdp_hist_irq_mask);
+	if (!(hw->irq_info->irq_mask & ndx_bit)) {
+		pr_warn("MDSS HW ndx=%d is NOT set\n", hw->hw_ndx);
 	} else {
-		mdss_res->irq_mask &= ~ndx_bit;
-		if (mdss_res->irq_mask == 0) {
-			mdss_res->irq_ena = false;
-			disable_irq_nosync(mdss_res->irq);
+		hw->irq_info->irq_mask &= ~ndx_bit;
+		if (hw->irq_info->irq_mask == 0) {
+			hw->irq_info->irq_ena = false;
+			disable_irq_nosync(hw->irq_info->irq);
 		}
 	}
 	spin_unlock(&mdss_lock);