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clk: qcom: mdss: remove references to 14nm

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Remove references to 14nm and replace them with thulium.

Change-Id: I8a3a86d3510bea71f19003bebe89318c2fb399d4
Signed-off-by: Vinu Deokaran <vinud@codeaurora.org>
This commit is contained in:
Vinu Deokaran 2015-01-29 15:48:55 -08:00 • committed by David Keitel
parent 21985f965e
commit ec1642743f
5 changed files with 72 additions and 72 deletions
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2
drivers/clk/msm/mdss/Makefile
View file

@ -9,4 +9,4 @@ obj-$(CONFIG_MSM_MDSS_PLL) += mdss-dsi-pll-thulium-util.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-edp-pll-28hpm.o obj-$(CONFIG_MSM_MDSS_PLL) += mdss-edp-pll-28hpm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-28hpm.o obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-28hpm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-20nm.o obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-20nm.o
obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-14nm.o obj-$(CONFIG_MSM_MDSS_PLL) += mdss-hdmi-pll-thulium.o

132
drivers/clk/msm/mdss/mdss-hdmi-pll-14nm.c → drivers/clk/msm/mdss/mdss-hdmi-pll-thulium.c
View file

@ -301,7 +301,7 @@ enum hdmi_pll_freqs {
HDMI_PCLK_MAX HDMI_PCLK_MAX
}; };
struct hdmi_14nm_phy_pll_reg_cfg { struct hdmi_thulium_phy_pll_reg_cfg {
u32 tx_l0_tx_band; u32 tx_l0_tx_band;
u32 tx_l1_tx_band; u32 tx_l1_tx_band;
u32 tx_l2_tx_band; u32 tx_l2_tx_band;
@ -355,7 +355,7 @@ static const u32 supported_freq_lut[HDMI_PCLK_MAX] = {
594000000 594000000
}; };
static const struct hdmi_14nm_phy_pll_reg_cfg reg_cfg_lut[HDMI_PCLK_MAX] = { static const struct hdmi_thulium_phy_pll_reg_cfg reg_cfg_lut[HDMI_PCLK_MAX] = {
/* 25200 KHz */ /* 25200 KHz */
{ {
@ -737,12 +737,12 @@ static const struct hdmi_14nm_phy_pll_reg_cfg reg_cfg_lut[HDMI_PCLK_MAX] = {
}, },
}; };
static inline struct hdmi_pll_vco_clk *to_hdmi_14nm_vco_clk(struct clk *clk) static inline struct hdmi_pll_vco_clk *to_hdmi_thulium_vco_clk(struct clk *clk)
{ {
return container_of(clk, struct hdmi_pll_vco_clk, c); return container_of(clk, struct hdmi_pll_vco_clk, c);
} }
static inline u64 hdmi_14nm_get_post_div_lt_2g(u64 bclk) static inline u64 hdmi_thulium_get_post_div_lt_2g(u64 bclk)
{ {
if (bclk >= HDMI_1334MHZ_BIT_CLK_HZ) if (bclk >= HDMI_1334MHZ_BIT_CLK_HZ)
return 3; return 3;
@ -760,7 +760,7 @@ static inline u64 hdmi_14nm_get_post_div_lt_2g(u64 bclk)
return HDMI_64B_ERR_VAL; return HDMI_64B_ERR_VAL;
} }
static inline u64 hdmi_14nm_get_coreclk_div_lt_2g(u64 bclk) static inline u64 hdmi_thulium_get_coreclk_div_lt_2g(u64 bclk)
{ {
if (bclk >= HDMI_1334MHZ_BIT_CLK_HZ) if (bclk >= HDMI_1334MHZ_BIT_CLK_HZ)
return 1; return 1;
@ -778,7 +778,7 @@ static inline u64 hdmi_14nm_get_coreclk_div_lt_2g(u64 bclk)
return HDMI_64B_ERR_VAL; return HDMI_64B_ERR_VAL;
} }
static inline u64 hdmi_14nm_get_coreclk_div_ratio(u64 clks_pll_divsel, static inline u64 hdmi_thulium_get_coreclk_div_ratio(u64 clks_pll_divsel,
u64 coreclk_div) u64 coreclk_div)
{ {
if (clks_pll_divsel == 0) if (clks_pll_divsel == 0)
@ -789,7 +789,7 @@ static inline u64 hdmi_14nm_get_coreclk_div_ratio(u64 clks_pll_divsel,
return HDMI_64B_ERR_VAL; return HDMI_64B_ERR_VAL;
} }
static inline u64 hdmi_14nm_get_tx_band(u64 bclk) static inline u64 hdmi_thulium_get_tx_band(u64 bclk)
{ {
if (bclk >= HDMI_2000MHZ_BIT_CLK_HZ) if (bclk >= HDMI_2000MHZ_BIT_CLK_HZ)
return 0; return 0;
@ -803,7 +803,7 @@ static inline u64 hdmi_14nm_get_tx_band(u64 bclk)
return HDMI_64B_ERR_VAL; return HDMI_64B_ERR_VAL;
} }
static inline u64 hdmi_14nm_get_hsclk(u64 fdata) static inline u64 hdmi_thulium_get_hsclk(u64 fdata)
{ {
if (fdata >= 8000000000) if (fdata >= 8000000000)
return 0; return 0;
@ -817,7 +817,7 @@ static inline u64 hdmi_14nm_get_hsclk(u64 fdata)
return HDMI_64B_ERR_VAL; return HDMI_64B_ERR_VAL;
} }
static inline u64 hdmi_14nm_get_cpctrl(u64 frac_start, bool gen_ssc) static inline u64 hdmi_thulium_get_cpctrl(u64 frac_start, bool gen_ssc)
{ {
if ((frac_start != 0) || if ((frac_start != 0) ||
(gen_ssc == true)) (gen_ssc == true))
@ -830,7 +830,7 @@ static inline u64 hdmi_14nm_get_cpctrl(u64 frac_start, bool gen_ssc)
return 0x23; return 0x23;
} }
static inline u64 hdmi_14nm_get_rctrl(u64 frac_start, bool gen_ssc) static inline u64 hdmi_thulium_get_rctrl(u64 frac_start, bool gen_ssc)
{ {
if ((frac_start != 0) || (gen_ssc == true)) if ((frac_start != 0) || (gen_ssc == true))
return 0x16; return 0x16;
@ -838,7 +838,7 @@ static inline u64 hdmi_14nm_get_rctrl(u64 frac_start, bool gen_ssc)
return 0x10; return 0x10;
} }
static inline u64 hdmi_14nm_get_cctrl(u64 frac_start, bool gen_ssc) static inline u64 hdmi_thulium_get_cctrl(u64 frac_start, bool gen_ssc)
{ {
if ((frac_start != 0) || (gen_ssc == true)) if ((frac_start != 0) || (gen_ssc == true))
return 0x28; return 0x28;
@ -846,7 +846,7 @@ static inline u64 hdmi_14nm_get_cctrl(u64 frac_start, bool gen_ssc)
return 0x1; return 0x1;
} }
static inline u64 hdmi_14nm_get_integloop_gain(u64 frac_start, bool gen_ssc) static inline u64 hdmi_thulium_get_integloop_gain(u64 frac_start, bool gen_ssc)
{ {
if ((frac_start != 0) || (gen_ssc == true)) if ((frac_start != 0) || (gen_ssc == true))
return 0x80; return 0x80;
@ -854,7 +854,7 @@ static inline u64 hdmi_14nm_get_integloop_gain(u64 frac_start, bool gen_ssc)
return 0xC4; return 0xC4;
} }
static inline u64 hdmi_14nm_get_vco_tune(u64 fdata, u64 div) static inline u64 hdmi_thulium_get_vco_tune(u64 fdata, u64 div)
{ {
u64 vco_tune; u64 vco_tune;
@ -866,7 +866,7 @@ static inline u64 hdmi_14nm_get_vco_tune(u64 fdata, u64 div)
return vco_tune; return vco_tune;
} }
static inline u64 hdmi_14nm_get_pll_cmp(u64 pll_cmp_cnt, u64 core_clk) static inline u64 hdmi_thulium_get_pll_cmp(u64 pll_cmp_cnt, u64 core_clk)
{ {
u64 pll_cmp; u64 pll_cmp;
u64 rem; u64 rem;
@ -879,8 +879,8 @@ static inline u64 hdmi_14nm_get_pll_cmp(u64 pll_cmp_cnt, u64 core_clk)
return pll_cmp; return pll_cmp;
} }
static int hdmi_14nm_calculate(u32 pix_clk, static int hdmi_thulium_calculate(u32 pix_clk,
struct hdmi_14nm_phy_pll_reg_cfg *cfg) struct hdmi_thulium_phy_pll_reg_cfg *cfg)
{ {
int rc = -EINVAL; int rc = -EINVAL;
u64 fdata, clk_divtx, tmds_clk; u64 fdata, clk_divtx, tmds_clk;
@ -913,16 +913,16 @@ static int hdmi_14nm_calculate(u32 pix_clk,
else else
tmds_clk = bclk; tmds_clk = bclk;
post_div_lt_2g = hdmi_14nm_get_post_div_lt_2g(bclk); post_div_lt_2g = hdmi_thulium_get_post_div_lt_2g(bclk);
if (post_div_lt_2g == HDMI_64B_ERR_VAL) if (post_div_lt_2g == HDMI_64B_ERR_VAL)
goto fail; goto fail;
coreclk_div1_lt_2g = hdmi_14nm_get_coreclk_div_lt_2g(bclk); coreclk_div1_lt_2g = hdmi_thulium_get_coreclk_div_lt_2g(bclk);
core_clk_div_ratio = hdmi_14nm_get_coreclk_div_ratio( core_clk_div_ratio = hdmi_thulium_get_coreclk_div_ratio(
HDMI_CLKS_PLL_DIVSEL, HDMI_CORECLK_DIV); HDMI_CLKS_PLL_DIVSEL, HDMI_CORECLK_DIV);
tx_band = hdmi_14nm_get_tx_band(bclk); tx_band = hdmi_thulium_get_tx_band(bclk);
if (tx_band == HDMI_64B_ERR_VAL) if (tx_band == HDMI_64B_ERR_VAL)
goto fail; goto fail;
@ -930,7 +930,7 @@ static int hdmi_14nm_calculate(u32 pix_clk,
if (bclk >= HDMI_2000MHZ_BIT_CLK_HZ) { if (bclk >= HDMI_2000MHZ_BIT_CLK_HZ) {
fdata = bclk; fdata = bclk;
hsclk = hdmi_14nm_get_hsclk(fdata); hsclk = hdmi_thulium_get_hsclk(fdata);
if (hsclk == HDMI_64B_ERR_VAL) if (hsclk == HDMI_64B_ERR_VAL)
goto fail; goto fail;
@ -945,7 +945,7 @@ static int hdmi_14nm_calculate(u32 pix_clk,
vco_freq = bclk * (post_div_lt_2g * tx_band_div_ratio); vco_freq = bclk * (post_div_lt_2g * tx_band_div_ratio);
fdata = vco_freq; fdata = vco_freq;
do_div(fdata, post_div_lt_2g); do_div(fdata, post_div_lt_2g);
hsclk = hdmi_14nm_get_hsclk(fdata); hsclk = hdmi_thulium_get_hsclk(fdata);
if (hsclk == HDMI_64B_ERR_VAL) if (hsclk == HDMI_64B_ERR_VAL)
goto fail; goto fail;
@ -967,15 +967,15 @@ static int hdmi_14nm_calculate(u32 pix_clk,
if (rem >= (pll_divisor >> 1)) if (rem >= (pll_divisor >> 1))
frac_start++; frac_start++;
cpctrl = hdmi_14nm_get_cpctrl(frac_start, false); cpctrl = hdmi_thulium_get_cpctrl(frac_start, false);
rctrl = hdmi_14nm_get_rctrl(frac_start, false); rctrl = hdmi_thulium_get_rctrl(frac_start, false);
cctrl = hdmi_14nm_get_cctrl(frac_start, false); cctrl = hdmi_thulium_get_cctrl(frac_start, false);
integloop_gain = hdmi_14nm_get_integloop_gain(frac_start, false); integloop_gain = hdmi_thulium_get_integloop_gain(frac_start, false);
vco_tune = hdmi_14nm_get_vco_tune(fdata, post_div_gt_2g); vco_tune = hdmi_thulium_get_vco_tune(fdata, post_div_gt_2g);
core_clk = clk_divtx; core_clk = clk_divtx;
do_div(core_clk, core_clk_div_ratio); do_div(core_clk, core_clk_div_ratio);
pll_cmp = hdmi_14nm_get_pll_cmp(1024, core_clk); pll_cmp = hdmi_thulium_get_pll_cmp(1024, core_clk);
/* Debug dump */ /* Debug dump */
pr_debug("%s: VCO freq: %llu\n", __func__, vco_freq); pr_debug("%s: VCO freq: %llu\n", __func__, vco_freq);
@ -1054,7 +1054,7 @@ static int hdmi_14nm_calculate(u32 pix_clk,
} }
cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0; cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0;
pr_debug("HDMI 14NM PLL: PLL Settings\n"); pr_debug("HDMI thulium PLL: PLL Settings\n");
pr_debug("PLL PARAM: tx_l0_tx_band = 0x%x\n", cfg->tx_l0_tx_band); pr_debug("PLL PARAM: tx_l0_tx_band = 0x%x\n", cfg->tx_l0_tx_band);
pr_debug("PLL PARAM: tx_l1_tx_band = 0x%x\n", cfg->tx_l1_tx_band); pr_debug("PLL PARAM: tx_l1_tx_band = 0x%x\n", cfg->tx_l1_tx_band);
pr_debug("PLL PARAM: tx_l2_tx_band = 0x%x\n", cfg->tx_l2_tx_band); pr_debug("PLL PARAM: tx_l2_tx_band = 0x%x\n", cfg->tx_l2_tx_band);
@ -1117,13 +1117,13 @@ fail:
return rc; return rc;
} }
static int hdmi_14nm_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk) static int hdmi_thulium_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk)
{ {
u32 i = 0; u32 i = 0;
int rc = 0; int rc = 0;
struct hdmi_pll_vco_clk *vco = to_hdmi_14nm_vco_clk(c); struct hdmi_pll_vco_clk *vco = to_hdmi_thulium_vco_clk(c);
struct mdss_pll_resources *io = vco->priv; struct mdss_pll_resources *io = vco->priv;
struct hdmi_14nm_phy_pll_reg_cfg cfg = {0}; struct hdmi_thulium_phy_pll_reg_cfg cfg = {0};
for (i = 0; i < HDMI_PCLK_MAX; i++) { for (i = 0; i < HDMI_PCLK_MAX; i++) {
if ((supported_freq_lut[i] >= (tmds_clk - 2000)) && if ((supported_freq_lut[i] >= (tmds_clk - 2000)) &&
@ -1137,7 +1137,7 @@ static int hdmi_14nm_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk)
pr_debug("%s: pixel clock %d is not present in LUT\n", __func__, pr_debug("%s: pixel clock %d is not present in LUT\n", __func__,
tmds_clk); tmds_clk);
rc = hdmi_14nm_calculate(tmds_clk, &cfg); rc = hdmi_thulium_calculate(tmds_clk, &cfg);
if (rc) { if (rc) {
pr_err("%s: PLL calculation failed\n", __func__); pr_err("%s: PLL calculation failed\n", __func__);
return rc; return rc;
@ -1346,7 +1346,7 @@ static int hdmi_14nm_phy_pll_set_clk_rate(struct clk *c, u32 tmds_clk)
return 0; return 0;
} }
static int hdmi_14nm_phy_ready_status(struct mdss_pll_resources *io) static int hdmi_thulium_phy_ready_status(struct mdss_pll_resources *io)
{ {
u32 status; u32 status;
int phy_ready = 0; int phy_ready = 0;
@ -1378,7 +1378,7 @@ static int hdmi_14nm_phy_ready_status(struct mdss_pll_resources *io)
return phy_ready; return phy_ready;
} }
static int hdmi_14nm_pll_lock_status(struct mdss_pll_resources *io) static int hdmi_thulium_pll_lock_status(struct mdss_pll_resources *io)
{ {
u32 status; u32 status;
int pll_locked = 0; int pll_locked = 0;
@ -1409,10 +1409,10 @@ static int hdmi_14nm_pll_lock_status(struct mdss_pll_resources *io)
return pll_locked; return pll_locked;
} }
static int hdmi_14nm_vco_enable(struct clk *c) static int hdmi_thulium_vco_enable(struct clk *c)
{ {
int rc; int rc;
struct hdmi_pll_vco_clk *vco = to_hdmi_14nm_vco_clk(c); struct hdmi_pll_vco_clk *vco = to_hdmi_thulium_vco_clk(c);
struct mdss_pll_resources *io = vco->priv; struct mdss_pll_resources *io = vco->priv;
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x1); MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x1);
@ -1421,7 +1421,7 @@ static int hdmi_14nm_vco_enable(struct clk *c)
MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x19); MDSS_PLL_REG_W(io->phy_base, HDMI_PHY_CFG, 0x19);
udelay(1); udelay(1);
rc = hdmi_14nm_pll_lock_status(io); rc = hdmi_thulium_pll_lock_status(io);
if (!rc) { if (!rc) {
pr_err("%s: PLL not locked\n", __func__); pr_err("%s: PLL not locked\n", __func__);
return rc; return rc;
@ -1447,7 +1447,7 @@ static int hdmi_14nm_vco_enable(struct clk *c)
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_STEP_SIZE2, 0x0); MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_STEP_SIZE2, 0x0);
MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_EN_CENTER, 0x2); MDSS_PLL_REG_W(io->pll_base, QSERDES_COM_SSC_EN_CENTER, 0x2);
rc = hdmi_14nm_phy_ready_status(io); rc = hdmi_thulium_phy_ready_status(io);
if (!rc) { if (!rc) {
pr_err("%s: PHY not READY\n", __func__); pr_err("%s: PHY not READY\n", __func__);
return rc; return rc;
@ -1462,9 +1462,9 @@ static int hdmi_14nm_vco_enable(struct clk *c)
return 0; return 0;
} }
static int hdmi_14nm_vco_set_rate(struct clk *c, unsigned long rate) static int hdmi_thulium_vco_set_rate(struct clk *c, unsigned long rate)
{ {
struct hdmi_pll_vco_clk *vco = to_hdmi_14nm_vco_clk(c); struct hdmi_pll_vco_clk *vco = to_hdmi_thulium_vco_clk(c);
struct mdss_pll_resources *io = vco->priv; struct mdss_pll_resources *io = vco->priv;
void __iomem *pll_base; void __iomem *pll_base;
void __iomem *phy_base; void __iomem *phy_base;
@ -1485,14 +1485,14 @@ static int hdmi_14nm_vco_set_rate(struct clk *c, unsigned long rate)
pr_debug("rate=%ld\n", rate); pr_debug("rate=%ld\n", rate);
rc = hdmi_14nm_phy_pll_set_clk_rate(c, rate); rc = hdmi_thulium_phy_pll_set_clk_rate(c, rate);
if (rc) if (rc)
pr_err("%s: Failed to set clk rate\n", __func__); pr_err("%s: Failed to set clk rate\n", __func__);
mdss_pll_resource_enable(io, false); mdss_pll_resource_enable(io, false);
if (set_power_dwn) if (set_power_dwn)
hdmi_14nm_vco_enable(c); hdmi_thulium_vco_enable(c);
vco->rate = rate; vco->rate = rate;
vco->rate_set = true; vco->rate_set = true;
@ -1500,14 +1500,14 @@ static int hdmi_14nm_vco_set_rate(struct clk *c, unsigned long rate)
return 0; return 0;
} }
static unsigned long hdmi_14nm_vco_get_rate(struct clk *c) static unsigned long hdmi_thulium_vco_get_rate(struct clk *c)
{ {
unsigned long freq = 0; unsigned long freq = 0;
return freq; return freq;
} }
static long hdmi_14nm_vco_round_rate(struct clk *c, unsigned long rate) static long hdmi_thulium_vco_round_rate(struct clk *c, unsigned long rate)
{ {
unsigned long rrate = rate; unsigned long rrate = rate;
@ -1516,16 +1516,16 @@ static long hdmi_14nm_vco_round_rate(struct clk *c, unsigned long rate)
return rrate; return rrate;
} }
static int hdmi_14nm_vco_prepare(struct clk *c) static int hdmi_thulium_vco_prepare(struct clk *c)
{ {
struct hdmi_pll_vco_clk *vco = to_hdmi_14nm_vco_clk(c); struct hdmi_pll_vco_clk *vco = to_hdmi_thulium_vco_clk(c);
struct mdss_pll_resources *io = vco->priv; struct mdss_pll_resources *io = vco->priv;
int ret = 0; int ret = 0;
pr_debug("rate=%ld\n", vco->rate); pr_debug("rate=%ld\n", vco->rate);
if (!vco->rate_set && vco->rate) if (!vco->rate_set && vco->rate)
ret = hdmi_14nm_vco_set_rate(c, vco->rate); ret = hdmi_thulium_vco_set_rate(c, vco->rate);
if (!ret) { if (!ret) {
ret = mdss_pll_resource_enable(io, true); ret = mdss_pll_resource_enable(io, true);
@ -1536,9 +1536,9 @@ static int hdmi_14nm_vco_prepare(struct clk *c)
return ret; return ret;
} }
static void hdmi_14nm_vco_unprepare(struct clk *c) static void hdmi_thulium_vco_unprepare(struct clk *c)
{ {
struct hdmi_pll_vco_clk *vco = to_hdmi_14nm_vco_clk(c); struct hdmi_pll_vco_clk *vco = to_hdmi_thulium_vco_clk(c);
struct mdss_pll_resources *io = vco->priv; struct mdss_pll_resources *io = vco->priv;
vco->rate_set = false; vco->rate_set = false;
@ -1559,10 +1559,10 @@ static void hdmi_14nm_vco_unprepare(struct clk *c)
io->pll_on = false; io->pll_on = false;
} }
static enum handoff hdmi_14nm_vco_handoff(struct clk *c) static enum handoff hdmi_thulium_vco_handoff(struct clk *c)
{ {
enum handoff ret = HANDOFF_DISABLED_CLK; enum handoff ret = HANDOFF_DISABLED_CLK;
struct hdmi_pll_vco_clk *vco = to_hdmi_14nm_vco_clk(c); struct hdmi_pll_vco_clk *vco = to_hdmi_thulium_vco_clk(c);
struct mdss_pll_resources *io = vco->priv; struct mdss_pll_resources *io = vco->priv;
if (is_gdsc_disabled(io)) if (is_gdsc_disabled(io))
@ -1575,10 +1575,10 @@ static enum handoff hdmi_14nm_vco_handoff(struct clk *c)
io->handoff_resources = true; io->handoff_resources = true;
if (hdmi_14nm_pll_lock_status(io)) { if (hdmi_thulium_pll_lock_status(io)) {
if (hdmi_14nm_phy_ready_status(io)) { if (hdmi_thulium_phy_ready_status(io)) {
io->pll_on = true; io->pll_on = true;
c->rate = hdmi_14nm_vco_get_rate(c); c->rate = hdmi_thulium_vco_get_rate(c);
ret = HANDOFF_ENABLED_CLK; ret = HANDOFF_ENABLED_CLK;
} else { } else {
io->handoff_resources = false; io->handoff_resources = false;
@ -1595,20 +1595,20 @@ static enum handoff hdmi_14nm_vco_handoff(struct clk *c)
return ret; return ret;
} }
static struct clk_ops hdmi_14nm_vco_clk_ops = { static struct clk_ops hdmi_thulium_vco_clk_ops = {
.enable = hdmi_14nm_vco_enable, .enable = hdmi_thulium_vco_enable,
.set_rate = hdmi_14nm_vco_set_rate, .set_rate = hdmi_thulium_vco_set_rate,
.get_rate = hdmi_14nm_vco_get_rate, .get_rate = hdmi_thulium_vco_get_rate,
.round_rate = hdmi_14nm_vco_round_rate, .round_rate = hdmi_thulium_vco_round_rate,
.prepare = hdmi_14nm_vco_prepare, .prepare = hdmi_thulium_vco_prepare,
.unprepare = hdmi_14nm_vco_unprepare, .unprepare = hdmi_thulium_vco_unprepare,
.handoff = hdmi_14nm_vco_handoff, .handoff = hdmi_thulium_vco_handoff,
}; };
static struct hdmi_pll_vco_clk hdmi_vco_clk = { static struct hdmi_pll_vco_clk hdmi_vco_clk = {
.c = { .c = {
.dbg_name = "hdmi_14nm_vco_clk", .dbg_name = "hdmi_thulium_vco_clk",
.ops = &hdmi_14nm_vco_clk_ops, .ops = &hdmi_thulium_vco_clk_ops,
CLK_INIT(hdmi_vco_clk.c), CLK_INIT(hdmi_vco_clk.c),
}, },
}; };
@ -1617,7 +1617,7 @@ static struct clk_lookup hdmipllcc_8996[] = {
CLK_LIST(hdmi_vco_clk), CLK_LIST(hdmi_vco_clk),
}; };
int hdmi_14nm_pll_clock_register(struct platform_device *pdev, int hdmi_thulium_pll_clock_register(struct platform_device *pdev,
struct mdss_pll_resources *pll_res) struct mdss_pll_resources *pll_res)
{ {
int rc = -ENOTSUPP; int rc = -ENOTSUPP;

2
drivers/clk/msm/mdss/mdss-hdmi-pll.h
View file

@ -39,6 +39,6 @@ int hdmi_pll_clock_register(struct platform_device *pdev,
int hdmi_20nm_pll_clock_register(struct platform_device *pdev, int hdmi_20nm_pll_clock_register(struct platform_device *pdev,
struct mdss_pll_resources *pll_res); struct mdss_pll_resources *pll_res);
int hdmi_14nm_pll_clock_register(struct platform_device *pdev, int hdmi_thulium_pll_clock_register(struct platform_device *pdev,
struct mdss_pll_resources *pll_res); struct mdss_pll_resources *pll_res);
#endif #endif

6
drivers/clk/msm/mdss/mdss-pll.c
View file

@ -157,7 +157,7 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8992")) { } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_8992")) {
pll_res->pll_interface_type = MDSS_HDMI_PLL_20NM; pll_res->pll_interface_type = MDSS_HDMI_PLL_20NM;
} else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_thulium")) { } else if (!strcmp(compatible_stream, "qcom,mdss_hdmi_pll_thulium")) {
pll_res->pll_interface_type = MDSS_HDMI_PLL_14NM; pll_res->pll_interface_type = MDSS_HDMI_PLL_THULIUM;
} else { } else {
goto err; goto err;
} }
@ -201,8 +201,8 @@ static int mdss_pll_clock_register(struct platform_device *pdev,
case MDSS_HDMI_PLL_20NM: case MDSS_HDMI_PLL_20NM:
rc = hdmi_20nm_pll_clock_register(pdev, pll_res); rc = hdmi_20nm_pll_clock_register(pdev, pll_res);
break; break;
case MDSS_HDMI_PLL_14NM: case MDSS_HDMI_PLL_THULIUM:
rc = hdmi_14nm_pll_clock_register(pdev, pll_res); rc = hdmi_thulium_pll_clock_register(pdev, pll_res);
break; break;
case MDSS_UNKNOWN_PLL: case MDSS_UNKNOWN_PLL:
default: default:

2
drivers/clk/msm/mdss/mdss-pll.h
View file

@ -35,7 +35,7 @@ enum {
MDSS_EDP_PLL, MDSS_EDP_PLL,
MDSS_HDMI_PLL, MDSS_HDMI_PLL,
MDSS_HDMI_PLL_20NM, MDSS_HDMI_PLL_20NM,
MDSS_HDMI_PLL_14NM, MDSS_HDMI_PLL_THULIUM,
MDSS_UNKNOWN_PLL, MDSS_UNKNOWN_PLL,
}; };