staging: comedi: ni_tio: tidy up Gi_Counting_Mode_Reg_Bits

Convert this enum into defines and rename all the CamelCase symbols.

For aesthetics, move the new defines so they are associated with the
register define.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

drivers/staging/comedi/drivers/ni_tio.c

@@ -116,59 +116,55 @@ TODO:
 #define NI_660X_LOGIC_LOW_GATE2_SEL	0x1f
 #define NI_660X_MAX_UP_DOWN_PIN		7
 
-static inline enum Gi_Counting_Mode_Reg_Bits
+static inline unsigned GI_ALT_SYNC(enum ni_gpct_variant variant)
-Gi_Alternate_Sync_Bit(enum ni_gpct_variant variant)
 {
 	switch (variant) {
 	case ni_gpct_variant_e_series:
 	default:
 		return 0;
 	case ni_gpct_variant_m_series:
-		return Gi_M_Series_Alternate_Sync_Bit;
+		return GI_M_ALT_SYNC;
 	case ni_gpct_variant_660x:
-		return Gi_660x_Alternate_Sync_Bit;
+		return GI_660X_ALT_SYNC;
 	}
 }
 
-static inline enum Gi_Counting_Mode_Reg_Bits
+static inline unsigned GI_PRESCALE_X2(enum ni_gpct_variant variant)
-Gi_Prescale_X2_Bit(enum ni_gpct_variant variant)
 {
 	switch (variant) {
 	case ni_gpct_variant_e_series:
 	default:
 		return 0;
 	case ni_gpct_variant_m_series:
-		return Gi_M_Series_Prescale_X2_Bit;
+		return GI_M_PRESCALE_X2;
 	case ni_gpct_variant_660x:
-		return Gi_660x_Prescale_X2_Bit;
+		return GI_660X_PRESCALE_X2;
 	}
 }
 
-static inline enum Gi_Counting_Mode_Reg_Bits
+static inline unsigned GI_PRESCALE_X8(enum ni_gpct_variant variant)
-Gi_Prescale_X8_Bit(enum ni_gpct_variant variant)
 {
 	switch (variant) {
 	case ni_gpct_variant_e_series:
 	default:
 		return 0;
 	case ni_gpct_variant_m_series:
-		return Gi_M_Series_Prescale_X8_Bit;
+		return GI_M_PRESCALE_X8;
 	case ni_gpct_variant_660x:
-		return Gi_660x_Prescale_X8_Bit;
+		return GI_660X_PRESCALE_X8;
 	}
 }
 
-static inline enum Gi_Counting_Mode_Reg_Bits
+static inline unsigned GI_HW_ARM_SEL_MASK(enum ni_gpct_variant variant)
-Gi_HW_Arm_Select_Mask(enum ni_gpct_variant variant)
 {
 	switch (variant) {
 	case ni_gpct_variant_e_series:
 	default:
 		return 0;
 	case ni_gpct_variant_m_series:
-		return Gi_M_Series_HW_Arm_Select_Mask;
+		return GI_M_HW_ARM_SEL_MASK;
 	case ni_gpct_variant_660x:
-		return Gi_660x_HW_Arm_Select_Mask;
+		return GI_660X_HW_ARM_SEL_MASK;
 	}
 }
 
@@ -254,9 +250,9 @@ static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
 	if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 	    Gi_Source_Polarity_Bit)
 		bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
-	if (counting_mode_bits & Gi_Prescale_X2_Bit(counter_dev->variant))
+	if (counting_mode_bits & GI_PRESCALE_X2(counter_dev->variant))
 		bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
-	if (counting_mode_bits & Gi_Prescale_X8_Bit(counter_dev->variant))
+	if (counting_mode_bits & GI_PRESCALE_X8(counter_dev->variant))
 		bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
 	return bits;
 }
@@ -401,17 +397,18 @@ static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync)
 	unsigned cidx = counter->counter_index;
 	const unsigned counting_mode_reg = NITIO_CNT_MODE_REG(cidx);
 	static const uint64_t min_normal_sync_period_ps = 25000;
+	unsigned mode;
 	uint64_t clock_period_ps;
 
 	if (ni_tio_counting_mode_registers_present(counter_dev) == 0)
 		return;
 
-	switch (ni_tio_get_soft_copy(counter, counting_mode_reg) &
+	mode = ni_tio_get_soft_copy(counter, counting_mode_reg);
-		Gi_Counting_Mode_Mask) {
+	switch (mode & GI_CNT_MODE_MASK) {
-	case Gi_Counting_Mode_QuadratureX1_Bits:
+	case GI_CNT_MODE_QUADX1:
-	case Gi_Counting_Mode_QuadratureX2_Bits:
+	case GI_CNT_MODE_QUADX2:
-	case Gi_Counting_Mode_QuadratureX4_Bits:
+	case GI_CNT_MODE_QUADX4:
-	case Gi_Counting_Mode_Sync_Source_Bits:
+	case GI_CNT_MODE_SYNC_SRC:
 		force_alt_sync = 1;
 		break;
 	default:
@@ -429,11 +426,11 @@ static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync)
 	if (force_alt_sync ||
 	    (clock_period_ps && clock_period_ps < min_normal_sync_period_ps)) {
 		ni_tio_set_bits(counter, counting_mode_reg,
-				Gi_Alternate_Sync_Bit(counter_dev->variant),
+				GI_ALT_SYNC(counter_dev->variant),
-				Gi_Alternate_Sync_Bit(counter_dev->variant));
+				GI_ALT_SYNC(counter_dev->variant));
 	} else {
 		ni_tio_set_bits(counter, counting_mode_reg,
-				Gi_Alternate_Sync_Bit(counter_dev->variant),
+				GI_ALT_SYNC(counter_dev->variant),
 				0x0);
 	}
 }
@@ -472,19 +469,15 @@ static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
 			mode_reg_mask, mode_reg_values);
 
 	if (ni_tio_counting_mode_registers_present(counter_dev)) {
-		unsigned counting_mode_bits = 0;
+		unsigned bits = 0;
 
-		counting_mode_bits |=
+		bits |= GI_CNT_MODE(mode >> NI_GPCT_COUNTING_MODE_SHIFT);
-		    (mode >> NI_GPCT_COUNTING_MODE_SHIFT) &
+		bits |= GI_INDEX_PHASE((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT));
-		    Gi_Counting_Mode_Mask;
-		counting_mode_bits |=
-		    ((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT) <<
-		     Gi_Index_Phase_Bitshift) & Gi_Index_Phase_Mask;
 		if (mode & NI_GPCT_INDEX_ENABLE_BIT)
-			counting_mode_bits |= Gi_Index_Mode_Bit;
+			bits |= GI_INDEX_MODE;
 		ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
-				Gi_Counting_Mode_Mask | Gi_Index_Phase_Mask |
+				GI_CNT_MODE_MASK | GI_INDEX_PHASE_MASK |
-				Gi_Index_Mode_Bit, counting_mode_bits);
+				GI_INDEX_MODE, bits);
 		ni_tio_set_sync_mode(counter, 0);
 	}
 
@@ -522,7 +515,10 @@ int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
 			break;
 		}
 		if (ni_tio_counting_mode_registers_present(counter_dev)) {
-			unsigned counting_mode_bits = 0;
+			unsigned bits = 0;
+			unsigned sel_mask;
+
+			sel_mask = GI_HW_ARM_SEL_MASK(counter_dev->variant);
 
 			switch (start_trigger) {
 			case NI_GPCT_ARM_IMMEDIATE:
@@ -535,25 +531,16 @@ int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
 					 * bits so we can figure out what
 					 * select later
 					 */
-					unsigned hw_arm_select_bits =
+					bits |= GI_HW_ARM_ENA |
-					    (start_trigger <<
+						(GI_HW_ARM_SEL(start_trigger) &
-					     Gi_HW_Arm_Select_Shift) &
+						 sel_mask);
-					    Gi_HW_Arm_Select_Mask
-					    (counter_dev->variant);
-
-					counting_mode_bits |=
-					    Gi_HW_Arm_Enable_Bit |
-					    hw_arm_select_bits;
 				} else {
 					return -EINVAL;
 				}
 				break;
 			}
 			ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
-					Gi_HW_Arm_Select_Mask
+					GI_HW_ARM_ENA | sel_mask, bits);
-					(counter_dev->variant) |
-					Gi_HW_Arm_Enable_Bit,
-					counting_mode_bits);
 		}
 	} else {
 		command_transient_bits |= Gi_Disarm_Bit;
@@ -735,17 +722,17 @@ static int ni_tio_set_clock_src(struct ni_gpct *counter,
 		case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 			break;
 		case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
-			bits |= Gi_Prescale_X2_Bit(counter_dev->variant);
+			bits |= GI_PRESCALE_X2(counter_dev->variant);
 			break;
 		case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
-			bits |= Gi_Prescale_X8_Bit(counter_dev->variant);
+			bits |= GI_PRESCALE_X8(counter_dev->variant);
 			break;
 		default:
 			return -EINVAL;
 		}
 		ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
-				Gi_Prescale_X2_Bit(counter_dev->variant) |
+				GI_PRESCALE_X2(counter_dev->variant) |
-				Gi_Prescale_X8_Bit(counter_dev->variant), bits);
+				GI_PRESCALE_X8(counter_dev->variant), bits);
 	}
 	counter->clock_period_ps = period_ns * 1000;
 	ni_tio_set_sync_mode(counter, 0);

drivers/staging/comedi/drivers/ni_tio_internal.h

@@ -30,6 +30,27 @@
 #define NITIO_LOADB_REG(x)		(NITIO_G0_LOADB + (x))
 #define NITIO_INPUT_SEL_REG(x)		(NITIO_G0_INPUT_SEL + (x))
 #define NITIO_CNT_MODE_REG(x)		(NITIO_G0_CNT_MODE + (x))
+#define GI_CNT_MODE(x)			(((x) & 0x7) << 0)
+#define GI_CNT_MODE_NORMAL		GI_CNT_MODE(0)
+#define GI_CNT_MODE_QUADX1		GI_CNT_MODE(1)
+#define GI_CNT_MODE_QUADX2		GI_CNT_MODE(2)
+#define GI_CNT_MODE_QUADX4		GI_CNT_MODE(3)
+#define GI_CNT_MODE_TWO_PULSE		GI_CNT_MODE(4)
+#define GI_CNT_MODE_SYNC_SRC		GI_CNT_MODE(6)
+#define GI_CNT_MODE_MASK		(7 << 0)
+#define GI_INDEX_MODE			(1 << 4)
+#define GI_INDEX_PHASE(x)		(((x) & 0x3) << 5)
+#define GI_INDEX_PHASE_MASK		(3 << 5)
+#define GI_HW_ARM_ENA			(1 << 7)
+#define GI_HW_ARM_SEL(x)		((x) << 8)
+#define GI_660X_HW_ARM_SEL_MASK		(0x7 << 8)
+#define GI_M_HW_ARM_SEL_MASK		(0x1f << 8)
+#define GI_660X_PRESCALE_X8		(1 << 12)
+#define GI_M_PRESCALE_X8		(1 << 13)
+#define GI_660X_ALT_SYNC		(1 << 13)
+#define GI_M_ALT_SYNC			(1 << 14)
+#define GI_660X_PRESCALE_X2		(1 << 14)
+#define GI_M_PRESCALE_X2		(1 << 15)
 #define NITIO_GATE2_REG(x)		(NITIO_G0_GATE2 + (x))
 #define NITIO_SHARED_STATUS_REG(x)	(NITIO_G01_STATUS + ((x) / 2))
 #define NITIO_RESET_REG(x)		(NITIO_G01_RESET + ((x) / 2))
@@ -68,41 +89,6 @@ enum Gi_Command_Reg_Bits {
 	Gi_Disarm_Copy_Bit = 0x8000
 };
 
-#define Gi_Index_Phase_Bitshift 5
-#define Gi_HW_Arm_Select_Shift 8
-enum Gi_Counting_Mode_Reg_Bits {
-	Gi_Counting_Mode_Mask = 0x7,
-	Gi_Counting_Mode_Normal_Bits = 0x0,
-	Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
-	Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
-	Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
-	Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
-	Gi_Counting_Mode_Sync_Source_Bits = 0x6,
-	Gi_Index_Mode_Bit = 0x10,
-	Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
-	Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
-	Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
-	Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
-	Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
-	/* from m-series example code, not documented in 660x register level
-	 * manual */
-	Gi_HW_Arm_Enable_Bit = 0x80,
-	/* from m-series example code, not documented in 660x register level
-	 * manual */
-	Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,
-	Gi_660x_Prescale_X8_Bit = 0x1000,
-	Gi_M_Series_Prescale_X8_Bit = 0x2000,
-	Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
-	/* must be set for clocks over 40MHz, which includes synchronous
-	 * counting and quadrature modes */
-	Gi_660x_Alternate_Sync_Bit = 0x2000,
-	Gi_M_Series_Alternate_Sync_Bit = 0x4000,
-	/* from m-series example code, not documented in 660x register level
-	 * manual */
-	Gi_660x_Prescale_X2_Bit = 0x4000,
-	Gi_M_Series_Prescale_X2_Bit = 0x8000,
-};
-
 #define Gi_Source_Select_Shift 2
 #define Gi_Gate_Select_Shift 7
 enum Gi_Input_Select_Bits {