staging: comedi: ni_tio: tidy up Gi_Counting_Mode_Reg_Bits
Convert this enum into defines and rename all the CamelCase symbols. For aesthetics, move the new defines so they are associated with the register define. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
56bd1ac708
commit
ed40487163
2 changed files with 63 additions and 90 deletions
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@ -116,59 +116,55 @@ TODO:
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#define NI_660X_LOGIC_LOW_GATE2_SEL 0x1f
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#define NI_660X_MAX_UP_DOWN_PIN 7
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static inline enum Gi_Counting_Mode_Reg_Bits
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Gi_Alternate_Sync_Bit(enum ni_gpct_variant variant)
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static inline unsigned GI_ALT_SYNC(enum ni_gpct_variant variant)
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{
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switch (variant) {
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case ni_gpct_variant_e_series:
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default:
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return 0;
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case ni_gpct_variant_m_series:
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return Gi_M_Series_Alternate_Sync_Bit;
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return GI_M_ALT_SYNC;
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case ni_gpct_variant_660x:
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return Gi_660x_Alternate_Sync_Bit;
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return GI_660X_ALT_SYNC;
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}
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}
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static inline enum Gi_Counting_Mode_Reg_Bits
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Gi_Prescale_X2_Bit(enum ni_gpct_variant variant)
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static inline unsigned GI_PRESCALE_X2(enum ni_gpct_variant variant)
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{
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switch (variant) {
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case ni_gpct_variant_e_series:
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default:
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return 0;
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case ni_gpct_variant_m_series:
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return Gi_M_Series_Prescale_X2_Bit;
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return GI_M_PRESCALE_X2;
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case ni_gpct_variant_660x:
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return Gi_660x_Prescale_X2_Bit;
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return GI_660X_PRESCALE_X2;
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}
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}
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static inline enum Gi_Counting_Mode_Reg_Bits
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Gi_Prescale_X8_Bit(enum ni_gpct_variant variant)
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static inline unsigned GI_PRESCALE_X8(enum ni_gpct_variant variant)
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{
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switch (variant) {
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case ni_gpct_variant_e_series:
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default:
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return 0;
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case ni_gpct_variant_m_series:
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return Gi_M_Series_Prescale_X8_Bit;
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return GI_M_PRESCALE_X8;
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case ni_gpct_variant_660x:
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return Gi_660x_Prescale_X8_Bit;
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return GI_660X_PRESCALE_X8;
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}
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}
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static inline enum Gi_Counting_Mode_Reg_Bits
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Gi_HW_Arm_Select_Mask(enum ni_gpct_variant variant)
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static inline unsigned GI_HW_ARM_SEL_MASK(enum ni_gpct_variant variant)
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{
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switch (variant) {
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case ni_gpct_variant_e_series:
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default:
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return 0;
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case ni_gpct_variant_m_series:
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return Gi_M_Series_HW_Arm_Select_Mask;
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return GI_M_HW_ARM_SEL_MASK;
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case ni_gpct_variant_660x:
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return Gi_660x_HW_Arm_Select_Mask;
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return GI_660X_HW_ARM_SEL_MASK;
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}
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}
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@ -254,9 +250,9 @@ static unsigned ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
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if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
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Gi_Source_Polarity_Bit)
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bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
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if (counting_mode_bits & Gi_Prescale_X2_Bit(counter_dev->variant))
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if (counting_mode_bits & GI_PRESCALE_X2(counter_dev->variant))
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bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
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if (counting_mode_bits & Gi_Prescale_X8_Bit(counter_dev->variant))
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if (counting_mode_bits & GI_PRESCALE_X8(counter_dev->variant))
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bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
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return bits;
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}
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@ -401,17 +397,18 @@ static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync)
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unsigned cidx = counter->counter_index;
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const unsigned counting_mode_reg = NITIO_CNT_MODE_REG(cidx);
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static const uint64_t min_normal_sync_period_ps = 25000;
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unsigned mode;
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uint64_t clock_period_ps;
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if (ni_tio_counting_mode_registers_present(counter_dev) == 0)
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return;
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switch (ni_tio_get_soft_copy(counter, counting_mode_reg) &
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Gi_Counting_Mode_Mask) {
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case Gi_Counting_Mode_QuadratureX1_Bits:
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case Gi_Counting_Mode_QuadratureX2_Bits:
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case Gi_Counting_Mode_QuadratureX4_Bits:
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case Gi_Counting_Mode_Sync_Source_Bits:
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mode = ni_tio_get_soft_copy(counter, counting_mode_reg);
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switch (mode & GI_CNT_MODE_MASK) {
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case GI_CNT_MODE_QUADX1:
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case GI_CNT_MODE_QUADX2:
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case GI_CNT_MODE_QUADX4:
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case GI_CNT_MODE_SYNC_SRC:
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force_alt_sync = 1;
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break;
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default:
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@ -429,11 +426,11 @@ static void ni_tio_set_sync_mode(struct ni_gpct *counter, int force_alt_sync)
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if (force_alt_sync ||
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(clock_period_ps && clock_period_ps < min_normal_sync_period_ps)) {
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ni_tio_set_bits(counter, counting_mode_reg,
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Gi_Alternate_Sync_Bit(counter_dev->variant),
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Gi_Alternate_Sync_Bit(counter_dev->variant));
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GI_ALT_SYNC(counter_dev->variant),
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GI_ALT_SYNC(counter_dev->variant));
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} else {
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ni_tio_set_bits(counter, counting_mode_reg,
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Gi_Alternate_Sync_Bit(counter_dev->variant),
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GI_ALT_SYNC(counter_dev->variant),
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0x0);
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}
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}
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@ -472,19 +469,15 @@ static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned mode)
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mode_reg_mask, mode_reg_values);
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if (ni_tio_counting_mode_registers_present(counter_dev)) {
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unsigned counting_mode_bits = 0;
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unsigned bits = 0;
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counting_mode_bits |=
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(mode >> NI_GPCT_COUNTING_MODE_SHIFT) &
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Gi_Counting_Mode_Mask;
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counting_mode_bits |=
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((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT) <<
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Gi_Index_Phase_Bitshift) & Gi_Index_Phase_Mask;
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bits |= GI_CNT_MODE(mode >> NI_GPCT_COUNTING_MODE_SHIFT);
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bits |= GI_INDEX_PHASE((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT));
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if (mode & NI_GPCT_INDEX_ENABLE_BIT)
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counting_mode_bits |= Gi_Index_Mode_Bit;
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bits |= GI_INDEX_MODE;
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ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
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Gi_Counting_Mode_Mask | Gi_Index_Phase_Mask |
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Gi_Index_Mode_Bit, counting_mode_bits);
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GI_CNT_MODE_MASK | GI_INDEX_PHASE_MASK |
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GI_INDEX_MODE, bits);
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ni_tio_set_sync_mode(counter, 0);
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}
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@ -522,7 +515,10 @@ int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
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break;
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}
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if (ni_tio_counting_mode_registers_present(counter_dev)) {
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unsigned counting_mode_bits = 0;
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unsigned bits = 0;
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unsigned sel_mask;
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sel_mask = GI_HW_ARM_SEL_MASK(counter_dev->variant);
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switch (start_trigger) {
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case NI_GPCT_ARM_IMMEDIATE:
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@ -535,25 +531,16 @@ int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger)
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* bits so we can figure out what
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* select later
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*/
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unsigned hw_arm_select_bits =
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(start_trigger <<
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Gi_HW_Arm_Select_Shift) &
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Gi_HW_Arm_Select_Mask
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(counter_dev->variant);
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counting_mode_bits |=
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Gi_HW_Arm_Enable_Bit |
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hw_arm_select_bits;
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bits |= GI_HW_ARM_ENA |
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(GI_HW_ARM_SEL(start_trigger) &
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sel_mask);
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} else {
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return -EINVAL;
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}
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break;
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}
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ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
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Gi_HW_Arm_Select_Mask
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(counter_dev->variant) |
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Gi_HW_Arm_Enable_Bit,
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counting_mode_bits);
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GI_HW_ARM_ENA | sel_mask, bits);
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}
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} else {
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command_transient_bits |= Gi_Disarm_Bit;
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@ -735,17 +722,17 @@ static int ni_tio_set_clock_src(struct ni_gpct *counter,
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case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
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break;
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case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
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bits |= Gi_Prescale_X2_Bit(counter_dev->variant);
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bits |= GI_PRESCALE_X2(counter_dev->variant);
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break;
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case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
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bits |= Gi_Prescale_X8_Bit(counter_dev->variant);
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bits |= GI_PRESCALE_X8(counter_dev->variant);
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break;
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default:
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return -EINVAL;
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}
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ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
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Gi_Prescale_X2_Bit(counter_dev->variant) |
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Gi_Prescale_X8_Bit(counter_dev->variant), bits);
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GI_PRESCALE_X2(counter_dev->variant) |
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GI_PRESCALE_X8(counter_dev->variant), bits);
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}
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counter->clock_period_ps = period_ns * 1000;
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ni_tio_set_sync_mode(counter, 0);
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@ -30,6 +30,27 @@
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#define NITIO_LOADB_REG(x) (NITIO_G0_LOADB + (x))
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#define NITIO_INPUT_SEL_REG(x) (NITIO_G0_INPUT_SEL + (x))
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#define NITIO_CNT_MODE_REG(x) (NITIO_G0_CNT_MODE + (x))
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#define GI_CNT_MODE(x) (((x) & 0x7) << 0)
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#define GI_CNT_MODE_NORMAL GI_CNT_MODE(0)
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#define GI_CNT_MODE_QUADX1 GI_CNT_MODE(1)
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#define GI_CNT_MODE_QUADX2 GI_CNT_MODE(2)
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#define GI_CNT_MODE_QUADX4 GI_CNT_MODE(3)
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#define GI_CNT_MODE_TWO_PULSE GI_CNT_MODE(4)
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#define GI_CNT_MODE_SYNC_SRC GI_CNT_MODE(6)
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#define GI_CNT_MODE_MASK (7 << 0)
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#define GI_INDEX_MODE (1 << 4)
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#define GI_INDEX_PHASE(x) (((x) & 0x3) << 5)
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#define GI_INDEX_PHASE_MASK (3 << 5)
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#define GI_HW_ARM_ENA (1 << 7)
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#define GI_HW_ARM_SEL(x) ((x) << 8)
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#define GI_660X_HW_ARM_SEL_MASK (0x7 << 8)
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#define GI_M_HW_ARM_SEL_MASK (0x1f << 8)
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#define GI_660X_PRESCALE_X8 (1 << 12)
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#define GI_M_PRESCALE_X8 (1 << 13)
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#define GI_660X_ALT_SYNC (1 << 13)
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#define GI_M_ALT_SYNC (1 << 14)
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#define GI_660X_PRESCALE_X2 (1 << 14)
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#define GI_M_PRESCALE_X2 (1 << 15)
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#define NITIO_GATE2_REG(x) (NITIO_G0_GATE2 + (x))
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#define NITIO_SHARED_STATUS_REG(x) (NITIO_G01_STATUS + ((x) / 2))
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#define NITIO_RESET_REG(x) (NITIO_G01_RESET + ((x) / 2))
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@ -68,41 +89,6 @@ enum Gi_Command_Reg_Bits {
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Gi_Disarm_Copy_Bit = 0x8000
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};
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#define Gi_Index_Phase_Bitshift 5
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#define Gi_HW_Arm_Select_Shift 8
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enum Gi_Counting_Mode_Reg_Bits {
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Gi_Counting_Mode_Mask = 0x7,
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Gi_Counting_Mode_Normal_Bits = 0x0,
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Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
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Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
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Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
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Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
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Gi_Counting_Mode_Sync_Source_Bits = 0x6,
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Gi_Index_Mode_Bit = 0x10,
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Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
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Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
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Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
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Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
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Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
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/* from m-series example code, not documented in 660x register level
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* manual */
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Gi_HW_Arm_Enable_Bit = 0x80,
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/* from m-series example code, not documented in 660x register level
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* manual */
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Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,
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Gi_660x_Prescale_X8_Bit = 0x1000,
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Gi_M_Series_Prescale_X8_Bit = 0x2000,
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Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
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/* must be set for clocks over 40MHz, which includes synchronous
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* counting and quadrature modes */
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Gi_660x_Alternate_Sync_Bit = 0x2000,
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Gi_M_Series_Alternate_Sync_Bit = 0x4000,
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/* from m-series example code, not documented in 660x register level
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* manual */
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Gi_660x_Prescale_X2_Bit = 0x4000,
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Gi_M_Series_Prescale_X2_Bit = 0x8000,
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};
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#define Gi_Source_Select_Shift 2
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#define Gi_Gate_Select_Shift 7
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enum Gi_Input_Select_Bits {
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