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drm/msm: reset TMDS clock ratio bit when disabling scrambler

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Currently, when scrambler is disabled the TMDS clock ratio bit
is left untouched. Ideally the sink should reset this bit during
hot plug OR no-signal cases. However, the HDMI spec requires this
bit to be explicitly reset by the source.

Add support to reset this bit during scrambler disable.

Change-Id: I092f6cae84653940e2bdb9100df5e384084cf938
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
This commit is contained in:
Abhinav Kumar 2017-08-03 17:08:09 -07:00
parent 58274ed8f1
commit ee79d2fe34
1 changed files with 9 additions and 0 deletions
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9
drivers/gpu/drm/msm/hdmi-staging/sde_hdmi_bridge.c
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@ -351,6 +351,7 @@ static int _sde_hdmi_bridge_setup_scrambler(struct hdmi *hdmi,
scrambler_on = true;
tmds_clock_ratio = 1;
} else {
tmds_clock_ratio = 0;
scrambler_on = connector->supports_scramble;
}
@ -396,6 +397,14 @@ static int _sde_hdmi_bridge_setup_scrambler(struct hdmi *hdmi,
rc = _sde_hdmi_bridge_setup_ddc_timers(hdmi,
HDMI_TX_DDC_TIMER_SCRAMBLER_STATUS, timeout_hsync);
} else {
/* reset tmds clock ratio */
rc = sde_hdmi_scdc_write(hdmi,
HDMI_TX_SCDC_TMDS_BIT_CLOCK_RATIO_UPDATE,
tmds_clock_ratio);
/* scdc write can fail if sink doesn't support SCDC */
if (rc && connector->scdc_present)
SDE_ERROR("SCDC present, TMDS clk ratio err\n");
sde_hdmi_scdc_write(hdmi, HDMI_TX_SCDC_SCRAMBLING_ENABLE, 0x0);
reg_val = hdmi_read(hdmi, REG_HDMI_CTRL);
reg_val &= ~BIT(28); /* Unset SCRAMBLER_EN bit */