diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index b58e2d2c7cc6..3ad4b6b5622d 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -1788,6 +1788,16 @@ qcom,msm-bus,num-cases = <22>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ <95 512 0 0>, <1 650 0 0>, /* No vote */ <95 512 922 0>, <1 650 1000 0>, /* PWM G1 */ <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */ @@ -1799,17 +1809,17 @@ <95 512 14752 0>, <1 650 1000 0>, /* PWM G4 L2 */ <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */ <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */ - <95 512 511181 0>, <1 650 1000 0>, /* HS G3 RA */ + <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RA */ <95 512 255591 0>, <1 650 1000 0>, /* HS G1 RA L2 */ <95 512 511181 0>, <1 650 1000 0>, /* HS G2 RA L2 */ - <95 512 1022362 0>, <1 650 1000 0>, /* HS G3 RA L2 */ + <95 512 4194304 0>, <1 650 204800 0>, /* HS G3 RA L2 */ <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */ <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */ - <95 512 596378 0>, <1 650 1000 0>, /* HS G3 RB */ + <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RB */ <95 512 298189 0>, <1 650 1000 0>, /* HS G1 RB L2 */ <95 512 596378 0>, <1 650 1000 0>, /* HS G2 RB L2 */ - <95 512 1192756 0>, <1 650 1000 0>, /* HS G3 RB L2 */ - <95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */ + <95 512 4194304 0>, <1 650 204800 0>, /* HS G3 RB L2 */ + <95 512 7643136 0>, <1 650 307200 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",