scsi: ufs-msm: modify PHY register configurations
Modify the PHY power up calibration values according to the latest hardware specification. Change-Id: I145dc8d5644c1914bb0fcb9c9b5790cf2b8de367 Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
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1 changed files with 19 additions and 8 deletions
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@ -341,7 +341,7 @@ static struct msm_ufs_phy_calibration phy_cal_table[] = {
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.reg_offset = UFS_PHY_POWER_DOWN_CONTROL,
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},
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{
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.cfg_value = 0x77,
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.cfg_value = 0xFF,
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.reg_offset = QSERDES_COM_PLL_CRCTRL,
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},
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{
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@ -353,11 +353,11 @@ static struct msm_ufs_phy_calibration phy_cal_table[] = {
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.reg_offset = QSERDES_COM_SYSCLK_EN_SEL,
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},
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{
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.cfg_value = 0x06,
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.cfg_value = 0x00,
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.reg_offset = QSERDES_COM_SYS_CLK_CTRL,
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},
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{
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.cfg_value = 0x02,
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.cfg_value = 0x03,
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.reg_offset = QSERDES_COM_PLL_CLKEPDIV,
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},
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{
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@ -397,7 +397,7 @@ static struct msm_ufs_phy_calibration phy_cal_table[] = {
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.reg_offset = QSERDES_COM_PLLLOCK_CMP_EN,
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},
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{
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.cfg_value = 0x14,
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.cfg_value = 0x10,
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.reg_offset = QSERDES_COM_RESETSM_CNTRL,
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},
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{
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@ -437,11 +437,11 @@ static struct msm_ufs_phy_calibration phy_cal_table[] = {
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.reg_offset = QSERDES_RX_CDR_CONTROL_QUARTER(1),
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},
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{
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.cfg_value = 0x80,
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.cfg_value = 0xC0,
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.reg_offset = QSERDES_RX_SIGDET_CNTRL(0),
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},
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{
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.cfg_value = 0x80,
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.cfg_value = 0xC0,
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.reg_offset = QSERDES_RX_SIGDET_CNTRL(1),
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},
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{
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@ -797,7 +797,7 @@ static struct msm_ufs_phy_calibration phy_cal_table[] = {
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.reg_offset = QSERDES_RX_EQ_CONTROL(0),
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},
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{
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.cfg_value = 0x71,
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.cfg_value = 0x73,
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.reg_offset = QSERDES_RX_RX_IQ_RXDET_EN(0),
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},
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{
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@ -877,7 +877,7 @@ static struct msm_ufs_phy_calibration phy_cal_table[] = {
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.reg_offset = QSERDES_RX_EQ_CONTROL(1),
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},
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{
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.cfg_value = 0x71,
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.cfg_value = 0x73,
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.reg_offset = QSERDES_RX_RX_IQ_RXDET_EN(1),
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},
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{
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@ -1252,10 +1252,21 @@ static int msm_ufs_hce_enable_notify(struct ufs_hba *hba, bool status)
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case PRE_CHANGE:
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/* Assert PHY reset and apply PHY calibration values */
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msm_ufs_assert_reset(hba);
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/* provide 1ms delay to let the reset pulse propagate */
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usleep_range(1000, 1100);
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msm_ufs_phy_calibrate(phy);
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/* De-assert PHY reset and start serdes */
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msm_ufs_deassert_reset(hba);
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/*
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* after reset deassertion, phy will need all ref clocks,
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* voltage, current to settle down before starting serdes.
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*/
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usleep_range(1000, 1100);
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msm_ufs_phy_start_serdes(phy);
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/* poll for PCS_READY for max. 1sec */
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