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scsi: ufs-msm: modify PHY register configurations

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Modify the PHY power up calibration values according to the
latest hardware specification.

Change-Id: I145dc8d5644c1914bb0fcb9c9b5790cf2b8de367
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
This commit is contained in:
Sujit Reddy Thumma 2013-09-11 10:22:29 +05:30 • committed by David Keitel
parent 5054a474e9
commit f0a4dc876f
1 changed files with 19 additions and 8 deletions
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27
drivers/scsi/ufs/ufs-msm.c
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@ -341,7 +341,7 @@ static struct msm_ufs_phy_calibration phy_cal_table[] = {
.reg_offset = UFS_PHY_POWER_DOWN_CONTROL, .reg_offset = UFS_PHY_POWER_DOWN_CONTROL,
}, },
{ {
.cfg_value = 0x77, .cfg_value = 0xFF,
.reg_offset = QSERDES_COM_PLL_CRCTRL, .reg_offset = QSERDES_COM_PLL_CRCTRL,
}, },
{ {
@ -353,11 +353,11 @@ static struct msm_ufs_phy_calibration phy_cal_table[] = {
.reg_offset = QSERDES_COM_SYSCLK_EN_SEL, .reg_offset = QSERDES_COM_SYSCLK_EN_SEL,
}, },
{ {
.cfg_value = 0x06, .cfg_value = 0x00,
.reg_offset = QSERDES_COM_SYS_CLK_CTRL, .reg_offset = QSERDES_COM_SYS_CLK_CTRL,
}, },
{ {
.cfg_value = 0x02, .cfg_value = 0x03,
.reg_offset = QSERDES_COM_PLL_CLKEPDIV, .reg_offset = QSERDES_COM_PLL_CLKEPDIV,
}, },
{ {
@ -397,7 +397,7 @@ static struct msm_ufs_phy_calibration phy_cal_table[] = {
.reg_offset = QSERDES_COM_PLLLOCK_CMP_EN, .reg_offset = QSERDES_COM_PLLLOCK_CMP_EN,
}, },
{ {
.cfg_value = 0x14, .cfg_value = 0x10,
.reg_offset = QSERDES_COM_RESETSM_CNTRL, .reg_offset = QSERDES_COM_RESETSM_CNTRL,
}, },
{ {
@ -437,11 +437,11 @@ static struct msm_ufs_phy_calibration phy_cal_table[] = {
.reg_offset = QSERDES_RX_CDR_CONTROL_QUARTER(1), .reg_offset = QSERDES_RX_CDR_CONTROL_QUARTER(1),
}, },
{ {
.cfg_value = 0x80, .cfg_value = 0xC0,
.reg_offset = QSERDES_RX_SIGDET_CNTRL(0), .reg_offset = QSERDES_RX_SIGDET_CNTRL(0),
}, },
{ {
.cfg_value = 0x80, .cfg_value = 0xC0,
.reg_offset = QSERDES_RX_SIGDET_CNTRL(1), .reg_offset = QSERDES_RX_SIGDET_CNTRL(1),
}, },
{ {
@ -797,7 +797,7 @@ static struct msm_ufs_phy_calibration phy_cal_table[] = {
.reg_offset = QSERDES_RX_EQ_CONTROL(0), .reg_offset = QSERDES_RX_EQ_CONTROL(0),
}, },
{ {
.cfg_value = 0x71, .cfg_value = 0x73,
.reg_offset = QSERDES_RX_RX_IQ_RXDET_EN(0), .reg_offset = QSERDES_RX_RX_IQ_RXDET_EN(0),
}, },
{ {
@ -877,7 +877,7 @@ static struct msm_ufs_phy_calibration phy_cal_table[] = {
.reg_offset = QSERDES_RX_EQ_CONTROL(1), .reg_offset = QSERDES_RX_EQ_CONTROL(1),
}, },
{ {
.cfg_value = 0x71, .cfg_value = 0x73,
.reg_offset = QSERDES_RX_RX_IQ_RXDET_EN(1), .reg_offset = QSERDES_RX_RX_IQ_RXDET_EN(1),
}, },
{ {
@ -1252,10 +1252,21 @@ static int msm_ufs_hce_enable_notify(struct ufs_hba *hba, bool status)
case PRE_CHANGE: case PRE_CHANGE:
/* Assert PHY reset and apply PHY calibration values */ /* Assert PHY reset and apply PHY calibration values */
msm_ufs_assert_reset(hba); msm_ufs_assert_reset(hba);
/* provide 1ms delay to let the reset pulse propagate */
usleep_range(1000, 1100);
msm_ufs_phy_calibrate(phy); msm_ufs_phy_calibrate(phy);
/* De-assert PHY reset and start serdes */ /* De-assert PHY reset and start serdes */
msm_ufs_deassert_reset(hba); msm_ufs_deassert_reset(hba);
/*
* after reset deassertion, phy will need all ref clocks,
* voltage, current to settle down before starting serdes.
*/
usleep_range(1000, 1100);
msm_ufs_phy_start_serdes(phy); msm_ufs_phy_start_serdes(phy);
/* poll for PCS_READY for max. 1sec */ /* poll for PCS_READY for max. 1sec */