From f0df83dc8b5057a545f267dbb0dfd622b67cac24 Mon Sep 17 00:00:00 2001 From: Chandan Uddaraju Date: Wed, 4 May 2016 15:49:26 -0700 Subject: [PATCH] ARM: dts: msm: setup external clock sources for DP clock on msmcobalt The DP RCGs exported by the MMSS clock controller (MMSS-CC) can be sourced out of the DP PLL which is outside the MMSS-CC. Set up these external clock sources to point to the DP PLL clocks. CRs-Fixed: 1009740 Change-Id: Ia8f60ba711770c26e5b5919d2c39d7986403ece6 Signed-off-by: Chandan Uddaraju --- arch/arm/boot/dts/qcom/msmcobalt.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index 2bd480fe25bc..ea25b61c17be 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -631,14 +631,17 @@ vdd_dig-supply = <&pmcobalt_s1_level>; clock-names = "xo", "gpll0", "gpll0_div", "pclk0_src", "pclk1_src", - "byte0_src", "byte1_src"; + "byte0_src", "byte1_src", + "dp_link_src", "dp_vco_div"; clocks = <&clock_gcc clk_cxo_clk_src>, <&clock_gcc clk_gpll0_out_main>, <&clock_gcc clk_gcc_mmss_gpll0_div_clk>, <&mdss_dsi0_pll clk_dsi0pll_pclk_mux>, <&mdss_dsi1_pll clk_dsi1pll_pclk_mux>, <&mdss_dsi0_pll clk_dsi0pll_byteclk_mux>, - <&mdss_dsi1_pll clk_dsi1pll_byteclk_mux>; + <&mdss_dsi1_pll clk_dsi1pll_byteclk_mux>, + <&mdss_dp_pll clk_dp_link_2x_clk_mux>, + <&mdss_dp_pll clk_vco_divided_clk_src>; #clock-cells = <1>; };