Merge "msm: camera: Add support for camera on version 2 of msmcobalt"
This commit is contained in:
commit
f18d5b789d
5 changed files with 289 additions and 6 deletions
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@ -13,6 +13,7 @@ Required properties:
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- "qcom,csiphy-v3.4.2"
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- "qcom,csiphy-v3.5"
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- "qcom,csiphy-v5.0"
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- "qcom,csiphy-v5.01"
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- reg : offset and length of the register set for the device
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for the csiphy operating in compatible mode.
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- reg-names : should specify relevant names to each reg property defined.
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111
arch/arm/boot/dts/qcom/msmcobalt-v2-camera.dtsi
Normal file
111
arch/arm/boot/dts/qcom/msmcobalt-v2-camera.dtsi
Normal file
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@ -0,0 +1,111 @@
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/*
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* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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&soc {
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qcom,csiphy@ca34000 {
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cell-index = <0>;
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compatible = "qcom,csiphy-v5.01", "qcom,csiphy";
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reg = <0xca34000 0x1000>;
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reg-names = "csiphy";
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interrupts = <0 78 0>;
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interrupt-names = "csiphy";
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clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
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<&clock_mmss clk_mmss_mnoc_ahb_clk>,
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<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
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<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
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<&clock_mmss clk_mmss_camss_ahb_clk>,
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<&clock_mmss clk_mmss_camss_top_ahb_clk>,
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<&clock_mmss clk_csi0_clk_src>,
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<&clock_mmss clk_mmss_camss_csi0_clk>,
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<&clock_mmss clk_mmss_camss_cphy_csid0_clk>,
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<&clock_mmss clk_csi0phytimer_clk_src>,
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<&clock_mmss clk_mmss_camss_csi0phytimer_clk>,
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<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
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<&clock_mmss clk_csiphy_clk_src>,
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<&clock_mmss clk_mmss_camss_csiphy0_clk>;
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clock-names = "mnoc_maxi", "mnoc_ahb",
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"bmic_smmu_ahb", "bmic_smmu_axi",
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"camss_ahb_clk", "camss_top_ahb_clk",
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"csi_src_clk", "csi_clk", "cphy_csid_clk",
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"csiphy_timer_src_clk", "csiphy_timer_clk",
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"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
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qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0
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0 256000000 0>;
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status = "ok";
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};
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qcom,csiphy@ca35000 {
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cell-index = <1>;
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compatible = "qcom,csiphy-v5.01", "qcom,csiphy";
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reg = <0xca35000 0x1000>;
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reg-names = "csiphy";
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interrupts = <0 79 0>;
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interrupt-names = "csiphy";
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clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
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<&clock_mmss clk_mmss_mnoc_ahb_clk>,
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<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
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<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
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<&clock_mmss clk_mmss_camss_ahb_clk>,
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<&clock_mmss clk_mmss_camss_top_ahb_clk>,
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<&clock_mmss clk_csi1_clk_src>,
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<&clock_mmss clk_mmss_camss_csi1_clk>,
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<&clock_mmss clk_mmss_camss_cphy_csid1_clk>,
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<&clock_mmss clk_csi1phytimer_clk_src>,
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<&clock_mmss clk_mmss_camss_csi1phytimer_clk>,
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<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
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<&clock_mmss clk_csiphy_clk_src>,
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<&clock_mmss clk_mmss_camss_csiphy1_clk>;
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clock-names = "mnoc_maxi", "mnoc_ahb",
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"bmic_smmu_ahb", "bmic_smmu_axi",
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"camss_ahb_clk", "camss_top_ahb_clk",
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"csi_src_clk", "csi_clk", "cphy_csid_clk",
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"csiphy_timer_src_clk", "csiphy_timer_clk",
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"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
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qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0
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0 256000000 0>;
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status = "ok";
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};
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qcom,csiphy@ca36000 {
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cell-index = <2>;
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compatible = "qcom,csiphy-v5.01", "qcom,csiphy";
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reg = <0xca36000 0x1000>;
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reg-names = "csiphy";
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interrupts = <0 80 0>;
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interrupt-names = "csiphy";
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clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
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<&clock_mmss clk_mmss_mnoc_ahb_clk>,
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<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
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<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
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<&clock_mmss clk_mmss_camss_ahb_clk>,
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<&clock_mmss clk_mmss_camss_top_ahb_clk>,
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<&clock_mmss clk_csi2_clk_src>,
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<&clock_mmss clk_mmss_camss_csi2_clk>,
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<&clock_mmss clk_mmss_camss_cphy_csid2_clk>,
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<&clock_mmss clk_csi2phytimer_clk_src>,
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<&clock_mmss clk_mmss_camss_csi2phytimer_clk>,
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<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
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<&clock_mmss clk_csiphy_clk_src>,
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<&clock_mmss clk_mmss_camss_csiphy2_clk>;
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clock-names = "mnoc_maxi", "mnoc_ahb",
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"bmic_smmu_ahb", "bmic_smmu_axi",
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"camss_ahb_clk", "camss_top_ahb_clk",
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"csi_src_clk", "csi_clk", "cphy_csid_clk",
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"csiphy_timer_src_clk", "csiphy_timer_clk",
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"camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk";
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qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0
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0 256000000 0>;
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status = "ok";
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};
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};
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@ -17,6 +17,7 @@
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*/
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#include "msmcobalt.dtsi"
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#include "msmcobalt-v2-camera.dtsi"
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/ {
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model = "Qualcomm Technologies, Inc. MSMCOBALT v2";
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@ -0,0 +1,160 @@
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/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef MSM_CSIPHY_5_0_1_HWREG_H
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#define MSM_CSIPHY_5_0_1_HWREG_H
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#define ULPM_WAKE_UP_TIMER_MODE 2
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#include <sensor/csiphy/msm_csiphy.h>
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struct csiphy_reg_parms_t csiphy_v5_0_1 = {
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.mipi_csiphy_interrupt_status0_addr = 0x8B0,
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.mipi_csiphy_interrupt_clear0_addr = 0x858,
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.mipi_csiphy_glbl_irq_cmd_addr = 0x828,
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.combo_clk_mask = 0x10,
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};
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struct csiphy_reg_3ph_parms_t csiphy_v5_0_1_3ph = {
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/*MIPI CSI PHY registers*/
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{0x814, 0xD5},
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{0x818, 0x1},
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{0x188, 0x7F},
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{0x18C, 0x7F},
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{0x190, 0x0},
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{0x104, 0x6},
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{0x108, 0x1},
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{0x10c, 0x12},
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{0x114, 0x20},
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{0x118, 0x3E},
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{0x11c, 0x41},
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{0x120, 0x41},
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{0x124, 0x7F},
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{0x128, 0x0},
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{0x12c, 0x0},
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{0x130, 0x1},
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{0x134, 0x0},
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{0x138, 0x0},
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{0x13C, 0x10},
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{0x140, 0x1},
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{0x144, 0x12},
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{0x148, 0xFE},
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{0x14C, 0x1},
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{0x154, 0x0},
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{0x15C, 0x23},
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{0x160, ULPM_WAKE_UP_TIMER_MODE},
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{0x164, 0x00},
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{0x168, 0xA0},
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{0x16C, 0x25},
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{0x170, 0x41},
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{0x174, 0x41},
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{0x178, 0x3E},
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{0x17C, 0x0},
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{0x180, 0x0},
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{0x184, 0x7F},
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{0x1cc, 0x41},
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{0x81c, 0x2},
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{0x82c, 0xFF},
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{0x830, 0xFF},
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{0x834, 0xFB},
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{0x838, 0xFF},
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{0x83c, 0x7F},
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{0x840, 0xFF},
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{0x844, 0xFF},
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{0x848, 0xEF},
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{0x84c, 0xFF},
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{0x850, 0xFF},
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{0x854, 0xFF},
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{0x28, 0x0},
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{0x800, 0x0},
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{0x4, 0xC},
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{0x8, 0x14},
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{0x8, 0x14},
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{0x10, 0x52},
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{0x14, 0x60},
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{0x14, 0x60},
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{0x1C, 0xa},
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{0x1c, 0xa},
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{0x38, 0x1},
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{0x3C, 0xB8},
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{0x3C, 0xB8},
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{0x14, 0x0},
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{0x14, 0x0},
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{0x700, 0xC0},
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{0x150, 0},
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{0x1dc, 0x51},
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{0x2C, 0x1},
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{0x34, 0xf},
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{0x728, 0x4},
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{0x0, 0x91},
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{0x70C, 0xA5},
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{0x38, 0xFE},
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{0x81c, 0x6},
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};
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struct csiphy_settings_t csiphy_combo_mode_v5_0_1 = {
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{
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{0x818, 0x1},
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{0x81c, 0x2},
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{0x004, 0x08},
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{0x704, 0x08},
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{0x204, 0x08},
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{0x404, 0x08},
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{0x604, 0x08},
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{0x02c, 0x1},
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{0x22c, 0x1},
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{0x42c, 0x1},
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{0x62c, 0x1},
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{0x72c, 0x1},
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{0x034, 0x0f},
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{0x234, 0x0f},
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{0x434, 0x0f},
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{0x634, 0x0f},
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{0x734, 0x0f},
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{0x01c, 0x0a},
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{0x21c, 0x0a},
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{0x41c, 0x0a},
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{0x61c, 0x0a},
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{0x71c, 0x0a},
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{0x014, 0x60},
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{0x214, 0x60},
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{0x414, 0x60},
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{0x614, 0x60},
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{0x714, 0x60},
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{0x728, 0x4},
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{0x428, 0x0a},
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{0x628, 0x0e},
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{0x03c, 0xb8},
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{0x73c, 0xb8},
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{0x23c, 0xb8},
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{0x43c, 0xb8},
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{0x63c, 0xb8},
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{0x000, 0x91},
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{0x700, 0x80},
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{0x200, 0x91},
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{0x400, 0x91},
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{0x600, 0x80},
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{0x70c, 0xA5},
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{0x60c, 0xA5},
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{0x010, 0x52},
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{0x710, 0x52},
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{0x210, 0x52},
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{0x410, 0x52},
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{0x610, 0x52},
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{0x038, 0xfe},
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{0x738, 0x1f},
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{0x238, 0xfe},
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{0x438, 0xfe},
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{0x638, 0x1f},
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}
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};
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#endif
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@ -26,6 +26,7 @@
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#include "include/msm_csiphy_3_4_2_hwreg.h"
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#include "include/msm_csiphy_3_5_hwreg.h"
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#include "include/msm_csiphy_5_0_hwreg.h"
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#include "include/msm_csiphy_5_0_1_hwreg.h"
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#include "cam_hw_ops.h"
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#define DBG_CSIPHY 0
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@ -40,7 +41,8 @@
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#define CSIPHY_VERSION_V32 0x32
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#define CSIPHY_VERSION_V342 0x342
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#define CSIPHY_VERSION_V35 0x35
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#define CSIPHY_VERSION_V50 0x50
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#define CSIPHY_VERSION_V50 0x500
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#define CSIPHY_VERSION_V501 0x501
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#define MSM_CSIPHY_DRV_NAME "msm_csiphy"
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#define CLK_LANE_OFFSET 1
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#define NUM_LANES_OFFSET 4
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@ -766,7 +768,7 @@ static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev,
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if (csiphy_dev->hw_version >= CSIPHY_VERSION_V30 &&
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csiphy_dev->clk_mux_base != NULL &&
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csiphy_dev->hw_version != CSIPHY_VERSION_V50) {
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csiphy_dev->hw_version < CSIPHY_VERSION_V50) {
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val = msm_camera_io_r(csiphy_dev->clk_mux_base);
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if (csiphy_params->combo_mode &&
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(csiphy_params->lane_mask & 0x18) == 0x18) {
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|
@ -789,7 +791,7 @@ static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev,
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rc = msm_camera_clk_enable(&csiphy_dev->pdev->dev,
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csiphy_dev->csiphy_3p_clk_info,
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csiphy_dev->csiphy_3p_clk, 2, true);
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if (csiphy_dev->hw_dts_version == CSIPHY_VERSION_V50)
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if (csiphy_dev->hw_dts_version >= CSIPHY_VERSION_V50)
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rc = msm_csiphy_3phase_lane_config_v50(
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csiphy_dev, csiphy_params);
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else
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|
@ -797,7 +799,7 @@ static int msm_csiphy_lane_config(struct csiphy_device *csiphy_dev,
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csiphy_params);
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csiphy_dev->num_irq_registers = 20;
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} else {
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if (csiphy_dev->hw_dts_version == CSIPHY_VERSION_V50)
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if (csiphy_dev->hw_dts_version >= CSIPHY_VERSION_V50)
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rc = msm_csiphy_2phase_lane_config_v50(
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csiphy_dev, csiphy_params);
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else
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|
@ -1201,7 +1203,7 @@ static int msm_csiphy_release(struct csiphy_device *csiphy_dev, void *arg)
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msm_camera_io_w(0x0,
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csiphy_dev->base + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
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mipi_csiphy_3ph_cmn_ctrl6.addr);
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if (csiphy_dev->hw_dts_version == CSIPHY_VERSION_V50)
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if (csiphy_dev->hw_dts_version >= CSIPHY_VERSION_V50)
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msm_camera_io_w(0x0,
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csiphy_dev->base +
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csiphy_dev->ctrl_reg->csiphy_3ph_reg.
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|
@ -1312,7 +1314,7 @@ static int msm_csiphy_release(struct csiphy_device *csiphy_dev, void *arg)
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msm_camera_io_w(0x0,
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csiphy_dev->base + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
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mipi_csiphy_3ph_cmn_ctrl6.addr);
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if (csiphy_dev->hw_dts_version == CSIPHY_VERSION_V50)
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if (csiphy_dev->hw_dts_version >= CSIPHY_VERSION_V50)
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msm_camera_io_w(0x0,
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csiphy_dev->base +
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csiphy_dev->ctrl_reg->csiphy_3ph_reg.
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|
@ -1694,6 +1696,14 @@ static int csiphy_probe(struct platform_device *pdev)
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|||
new_csiphy_dev->csiphy_3phase = CSI_3PHASE_HW;
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||||
new_csiphy_dev->ctrl_reg->csiphy_combo_mode_settings =
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csiphy_combo_mode_v5_0;
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} else if (of_device_is_compatible(new_csiphy_dev->pdev->dev.of_node,
|
||||
"qcom,csiphy-v5.01")) {
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||||
new_csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_v5_0_1_3ph;
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new_csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v5_0_1;
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new_csiphy_dev->hw_dts_version = CSIPHY_VERSION_V501;
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||||
new_csiphy_dev->csiphy_3phase = CSI_3PHASE_HW;
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||||
new_csiphy_dev->ctrl_reg->csiphy_combo_mode_settings =
|
||||
csiphy_combo_mode_v5_0_1;
|
||||
} else {
|
||||
pr_err("%s:%d, invalid hw version : 0x%x\n", __func__, __LINE__,
|
||||
new_csiphy_dev->hw_dts_version);
|
||||
|
|
Loading…
Add table
Reference in a new issue