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drm/radeon: add RADEON_GEM_NO_CPU_ACCESS BO creation flag (v4)

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Allows pinning of buffers in the non-CPU visible portion of
vram.

v2: incorporate Michel's comments.
v3: rebase on Michel's patch
v4: rebase on Michel's v2 patch

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Alex Deucher 2014-08-28 10:59:05 -04:00
parent b76ee67a23
commit f266f04d33
2 changed files with 3 additions and 0 deletions
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1
drivers/gpu/drm/radeon/radeon_object.c
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@ -313,6 +313,7 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
for (i = 0; i < bo->placement.num_placement; i++) { for (i = 0; i < bo->placement.num_placement; i++) {
/* force to pin into visible video ram */ /* force to pin into visible video ram */
if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
!(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
(!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
bo->placements[i].lpfn = bo->placements[i].lpfn =
bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;

2
include/uapi/drm/radeon_drm.h
View file

@ -803,6 +803,8 @@ struct drm_radeon_gem_info {
#define RADEON_GEM_GTT_WC (1 << 2) #define RADEON_GEM_GTT_WC (1 << 2)
/* BO is expected to be accessed by the CPU */ /* BO is expected to be accessed by the CPU */
#define RADEON_GEM_CPU_ACCESS (1 << 3) #define RADEON_GEM_CPU_ACCESS (1 << 3)
/* CPU access is not expected to work for this BO */
#define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
struct drm_radeon_gem_create { struct drm_radeon_gem_create {
uint64_t size; uint64_t size;