Merge "ASoC: wcd934x: Update surge recovery for version 1.1"
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commit
f2a510bc7a
1 changed files with 71 additions and 4 deletions
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@ -4362,6 +4362,9 @@ static const struct reg_sequence tavil_hph_reset_tbl[] = {
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{ WCD934X_HPH_RDAC_LDO_CTL, 0x33 },
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{ WCD934X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00 },
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{ WCD934X_HPH_REFBUFF_UHQA_CTL, 0xA8 },
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};
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static const struct reg_sequence tavil_hph_reset_tbl_1_0[] = {
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{ WCD934X_HPH_REFBUFF_LP_CTL, 0x0A },
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{ WCD934X_HPH_L_DAC_CTL, 0x00 },
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{ WCD934X_HPH_R_DAC_CTL, 0x00 },
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@ -4383,6 +4386,28 @@ static const struct reg_sequence tavil_hph_reset_tbl[] = {
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{ WCD934X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00 },
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};
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static const struct reg_sequence tavil_hph_reset_tbl_1_1[] = {
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{ WCD934X_HPH_REFBUFF_LP_CTL, 0x0E },
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{ WCD934X_HPH_L_DAC_CTL, 0x00 },
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{ WCD934X_HPH_R_DAC_CTL, 0x00 },
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{ WCD934X_HPH_NEW_ANA_HPH2, 0x00 },
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{ WCD934X_HPH_NEW_ANA_HPH3, 0x00 },
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{ WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40 },
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{ WCD934X_HPH_NEW_INT_RDAC_HD2_CTL, 0x81 },
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{ WCD934X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10 },
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{ WCD934X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00 },
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{ WCD934X_HPH_NEW_INT_RDAC_MISC1, 0x81 },
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{ WCD934X_HPH_NEW_INT_PA_MISC1, 0x22 },
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{ WCD934X_HPH_NEW_INT_PA_MISC2, 0x00 },
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{ WCD934X_HPH_NEW_INT_PA_RDAC_MISC, 0x00 },
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{ WCD934X_HPH_NEW_INT_HPH_TIMER1, 0xFE },
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{ WCD934X_HPH_NEW_INT_HPH_TIMER2, 0x2 },
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{ WCD934X_HPH_NEW_INT_HPH_TIMER3, 0x4e},
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{ WCD934X_HPH_NEW_INT_HPH_TIMER4, 0x54 },
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{ WCD934X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00 },
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{ WCD934X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00 },
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};
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static const struct tavil_reg_mask_val tavil_pa_disable[] = {
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{ WCD934X_CDC_RX1_RX_PATH_CTL, 0x30, 0x10 }, /* RX1 mute enable */
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{ WCD934X_CDC_RX2_RX_PATH_CTL, 0x30, 0x10 }, /* RX2 mute enable */
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@ -4408,6 +4433,7 @@ static const struct tavil_reg_mask_val tavil_ocp_en_seq_1[] = {
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/* LO-HIFI */
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static const struct tavil_reg_mask_val tavil_pre_pa_en_lohifi[] = {
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{ WCD934X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00 },
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{ WCD934X_FLYBACK_VNEG_CTRL_4, 0xf0, 0x80 },
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{ WCD934X_HPH_NEW_INT_PA_MISC2, 0x20, 0x20 },
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{ WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL, 0xf0, 0x40 },
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{ WCD934X_HPH_CNP_WG_CTL, 0x80, 0x00 },
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@ -4449,6 +4475,7 @@ static void tavil_codec_hph_reg_recover(struct tavil_priv *tavil,
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struct regmap *map, int pa_status)
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{
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int i;
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unsigned int reg;
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blocking_notifier_call_chain(&tavil->mbhc->notifier,
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WCD_EVENT_OCP_OFF,
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@ -4470,6 +4497,12 @@ static void tavil_codec_hph_reg_recover(struct tavil_priv *tavil,
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/* Restore to HW defaults */
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regmap_multi_reg_write(map, tavil_hph_reset_tbl,
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ARRAY_SIZE(tavil_hph_reset_tbl));
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if (TAVIL_IS_1_1(tavil->wcd9xxx))
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regmap_multi_reg_write(map, tavil_hph_reset_tbl_1_1,
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ARRAY_SIZE(tavil_hph_reset_tbl_1_1));
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if (TAVIL_IS_1_0(tavil->wcd9xxx))
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regmap_multi_reg_write(map, tavil_hph_reset_tbl_1_0,
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ARRAY_SIZE(tavil_hph_reset_tbl_1_0));
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for (i = 0; i < ARRAY_SIZE(tavil_ocp_en_seq); i++)
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regmap_write_bits(map, tavil_ocp_en_seq[i].reg,
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@ -4483,13 +4516,23 @@ pa_en_restore:
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__func__, pa_status);
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/* Disable PA and other registers before restoring */
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for (i = 0; i < ARRAY_SIZE(tavil_pa_disable); i++)
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for (i = 0; i < ARRAY_SIZE(tavil_pa_disable); i++) {
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if (TAVIL_IS_1_1(tavil->wcd9xxx) &&
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(tavil_pa_disable[i].reg == WCD934X_HPH_CNP_WG_CTL))
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continue;
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regmap_write_bits(map, tavil_pa_disable[i].reg,
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tavil_pa_disable[i].mask,
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tavil_pa_disable[i].val);
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}
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regmap_multi_reg_write(map, tavil_hph_reset_tbl,
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ARRAY_SIZE(tavil_hph_reset_tbl));
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if (TAVIL_IS_1_1(tavil->wcd9xxx))
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regmap_multi_reg_write(map, tavil_hph_reset_tbl_1_1,
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ARRAY_SIZE(tavil_hph_reset_tbl_1_1));
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if (TAVIL_IS_1_0(tavil->wcd9xxx))
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regmap_multi_reg_write(map, tavil_hph_reset_tbl_1_0,
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ARRAY_SIZE(tavil_hph_reset_tbl_1_0));
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for (i = 0; i < ARRAY_SIZE(tavil_ocp_en_seq_1); i++)
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regmap_write_bits(map, tavil_ocp_en_seq_1[i].reg,
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@ -4497,17 +4540,37 @@ pa_en_restore:
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tavil_ocp_en_seq_1[i].val);
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if (tavil->hph_mode == CLS_H_LOHIFI) {
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for (i = 0; i < ARRAY_SIZE(tavil_pre_pa_en_lohifi); i++)
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for (i = 0; i < ARRAY_SIZE(tavil_pre_pa_en_lohifi); i++) {
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reg = tavil_pre_pa_en_lohifi[i].reg;
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if ((TAVIL_IS_1_1(tavil->wcd9xxx)) &&
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((reg == WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL) ||
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(reg == WCD934X_HPH_CNP_WG_CTL) ||
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(reg == WCD934X_HPH_REFBUFF_LP_CTL)))
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continue;
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regmap_write_bits(map,
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tavil_pre_pa_en_lohifi[i].reg,
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tavil_pre_pa_en_lohifi[i].mask,
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tavil_pre_pa_en_lohifi[i].val);
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}
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} else {
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for (i = 0; i < ARRAY_SIZE(tavil_pre_pa_en); i++)
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for (i = 0; i < ARRAY_SIZE(tavil_pre_pa_en); i++) {
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reg = tavil_pre_pa_en[i].reg;
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if ((TAVIL_IS_1_1(tavil->wcd9xxx)) &&
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((reg == WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL) ||
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(reg == WCD934X_HPH_CNP_WG_CTL) ||
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(reg == WCD934X_HPH_REFBUFF_LP_CTL)))
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continue;
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regmap_write_bits(map, tavil_pre_pa_en[i].reg,
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tavil_pre_pa_en[i].mask,
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tavil_pre_pa_en[i].val);
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}
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}
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if (TAVIL_IS_1_1(tavil->wcd9xxx)) {
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regmap_write(map, WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x84);
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regmap_write(map, WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x84);
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}
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regmap_write_bits(map, WCD934X_ANA_HPH, 0x0C, pa_status & 0x0C);
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regmap_write_bits(map, WCD934X_ANA_HPH, 0x30, 0x30);
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/* wait for 100usec after HPH DAC is enabled */
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@ -4516,10 +4579,14 @@ pa_en_restore:
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/* Sleep for 7msec after PA is enabled */
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usleep_range(7000, 7100);
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for (i = 0; i < ARRAY_SIZE(tavil_post_pa_en); i++)
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for (i = 0; i < ARRAY_SIZE(tavil_post_pa_en); i++) {
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if ((TAVIL_IS_1_1(tavil->wcd9xxx)) &&
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(tavil_post_pa_en[i].reg == WCD934X_HPH_CNP_WG_CTL))
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continue;
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regmap_write_bits(map, tavil_post_pa_en[i].reg,
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tavil_post_pa_en[i].mask,
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tavil_post_pa_en[i].val);
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}
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end:
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tavil->mbhc->is_hph_recover = true;
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