ARM: dts: msm: Set the rate for camss vfe clock on SDM660 & SDM630
Under ispif node set clock rate for camss vfe clock since after xo shutdown this clock cannot be enabled without setting rate first. Also, enable vfe clk src before camss clock. Change-Id: I3f80837abbb3f7d788db5b736cdb0d9816d7da14 Signed-off-by: Venu Yeshala <vyeshala@codeaurora.org>
This commit is contained in:
Venu Yeshala
Gerrit - the friendly Code Review server
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630218f710
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f38e93e11f
2 changed files with 44 additions and 40 deletions
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@ -451,11 +451,11 @@
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<&clock_mmss MMSS_CAMSS_CSI1_CLK>,
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<&clock_mmss MMSS_CAMSS_CSI2_CLK>,
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<&clock_mmss MMSS_CAMSS_CSI3_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE0_CLK>,
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<&clock_mmss VFE0_CLK_SRC>,
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<&clock_mmss MMSS_CAMSS_VFE0_CLK>,
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<&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE1_CLK>,
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<&clock_mmss VFE1_CLK_SRC>,
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<&clock_mmss MMSS_CAMSS_VFE1_CLK>,
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<&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>;
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clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
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"camss_ahb_clk",
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@ -468,10 +468,12 @@
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"csi2_pix_clk", "csi3_pix_clk",
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"camss_csi0_clk", "camss_csi1_clk",
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"camss_csi2_clk", "camss_csi3_clk",
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"vfe0_clk_src",
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"camss_vfe_vfe0_clk",
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"vfe0_clk_src", "camss_csi_vfe0_clk",
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"camss_csi_vfe0_clk",
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"vfe1_clk_src",
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"camss_vfe_vfe1_clk",
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"vfe1_clk_src", "camss_csi_vfe1_clk";
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"camss_csi_vfe1_clk";
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qcom,clock-rates = <0 0 0 0 0
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0 0 0 0
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0 0 0 0
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@ -490,10 +492,10 @@
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"NO_SET_RATE", "NO_SET_RATE",
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"NO_SET_RATE", "NO_SET_RATE",
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"NO_SET_RATE", "NO_SET_RATE",
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"NO_SET_RATE",
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"INIT_RATE", "NO_SET_RATE",
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"NO_SET_RATE",
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"INIT_RATE", "NO_SET_RATE";
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"INIT_RATE",
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"NO_SET_RATE", "NO_SET_RATE",
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"INIT_RATE",
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"NO_SET_RATE", "NO_SET_RATE";
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status = "ok";
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};
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@ -516,23 +518,23 @@
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<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
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<&clock_mmss MMSS_CAMSS_AHB_CLK>,
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<&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
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<&clock_mmss VFE0_CLK_SRC>,
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<&clock_mmss MMSS_CAMSS_VFE0_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE0_STREAM_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE0_AHB_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>,
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<&clock_mmss VFE0_CLK_SRC>,
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<&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>;
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clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
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"bimc_smmu_ahb_clk", "bimc_smmu_axi_clk",
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"camss_ahb_clk", "camss_top_ahb_clk",
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"camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src",
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"camss_vfe_clk", "camss_vfe_stream_clk",
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"camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk",
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"camss_vfe_vbif_axi_clk", "vfe_clk_src",
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"camss_vfe_vbif_axi_clk",
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"camss_csi_vfe_clk";
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qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 404000000 0
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0 0 0 0 0 0 0 0 0 0 0 480000000 0
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0 0 0 0 0 0 0 0 0 0 0 576000000 0>;
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qcom,clock-rates = <0 0 0 0 0 0 404000000 0 0 0 0 0 0
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0 0 0 0 0 0 480000000 0 0 0 0 0 0
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0 0 0 0 0 0 576000000 0 0 0 0 0 0>;
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status = "ok";
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qos-entries = <8>;
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qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418
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@ -597,23 +599,23 @@
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<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
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<&clock_mmss MMSS_CAMSS_AHB_CLK>,
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<&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
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<&clock_mmss VFE1_CLK_SRC>,
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<&clock_mmss MMSS_CAMSS_VFE1_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE1_STREAM_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE1_AHB_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>,
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<&clock_mmss VFE1_CLK_SRC>,
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<&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>;
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clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
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"bimc_smmu_ahb_clk", "bimc_smmu_axi_clk",
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"camss_ahb_clk", "camss_top_ahb_clk",
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"camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src",
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"camss_vfe_clk", "camss_vfe_stream_clk",
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"camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk",
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"camss_vfe_vbif_axi_clk", "vfe_clk_src",
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"camss_vfe_vbif_axi_clk",
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"camss_csi_vfe_clk";
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qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 404000000 0
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0 0 0 0 0 0 0 0 0 0 0 480000000 0
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0 0 0 0 0 0 0 0 0 0 0 576000000 0>;
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qcom,clock-rates = <0 0 0 0 0 0 404000000 0 0 0 0 0 0
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0 0 0 0 0 0 480000000 0 0 0 0 0 0
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0 0 0 0 0 0 576000000 0 0 0 0 0 0>;
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status = "ok";
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qos-entries = <8>;
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qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418
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@ -454,11 +454,11 @@
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<&clock_mmss MMSS_CAMSS_CSI1_CLK>,
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<&clock_mmss MMSS_CAMSS_CSI2_CLK>,
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<&clock_mmss MMSS_CAMSS_CSI3_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE0_CLK>,
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<&clock_mmss VFE0_CLK_SRC>,
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<&clock_mmss MMSS_CAMSS_VFE0_CLK>,
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<&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE1_CLK>,
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<&clock_mmss VFE1_CLK_SRC>,
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<&clock_mmss MMSS_CAMSS_VFE1_CLK>,
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<&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>;
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clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
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"camss_ahb_clk",
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@ -471,10 +471,12 @@
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"csi2_pix_clk", "csi3_pix_clk",
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"camss_csi0_clk", "camss_csi1_clk",
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"camss_csi2_clk", "camss_csi3_clk",
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"vfe0_clk_src",
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"camss_vfe_vfe0_clk",
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"vfe0_clk_src", "camss_csi_vfe0_clk",
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"camss_csi_vfe0_clk",
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"vfe1_clk_src",
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"camss_vfe_vfe1_clk",
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"vfe1_clk_src", "camss_csi_vfe1_clk";
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"camss_csi_vfe1_clk";
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qcom,clock-rates = <0 0 0 0 0
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0 0 0 0
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0 0 0 0
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@ -493,10 +495,10 @@
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"NO_SET_RATE", "NO_SET_RATE",
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"NO_SET_RATE", "NO_SET_RATE",
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"NO_SET_RATE", "NO_SET_RATE",
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"NO_SET_RATE",
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"INIT_RATE", "NO_SET_RATE",
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"NO_SET_RATE",
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"INIT_RATE", "NO_SET_RATE";
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"INIT_RATE",
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"NO_SET_RATE", "NO_SET_RATE",
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"INIT_RATE",
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"NO_SET_RATE", "NO_SET_RATE";
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status = "ok";
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};
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@ -518,23 +520,23 @@
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<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
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<&clock_mmss MMSS_CAMSS_AHB_CLK>,
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<&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
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<&clock_mmss VFE0_CLK_SRC>,
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<&clock_mmss MMSS_CAMSS_VFE0_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE0_STREAM_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE0_AHB_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>,
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<&clock_mmss VFE0_CLK_SRC>,
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<&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>;
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clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
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"bimc_smmu_ahb_clk", "bimc_smmu_axi_clk",
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"camss_ahb_clk", "camss_top_ahb_clk",
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"camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src",
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"camss_vfe_clk", "camss_vfe_stream_clk",
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"camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk",
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"camss_vfe_vbif_axi_clk", "vfe_clk_src",
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"camss_vfe_vbif_axi_clk",
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"camss_csi_vfe_clk";
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qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 404000000 0
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0 0 0 0 0 0 0 0 0 0 0 480000000 0
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0 0 0 0 0 0 0 0 0 0 0 576000000 0>;
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qcom,clock-rates = <0 0 0 0 0 0 404000000 0 0 0 0 0 0
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0 0 0 0 0 0 480000000 0 0 0 0 0 0
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0 0 0 0 0 0 576000000 0 0 0 0 0 0>;
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status = "ok";
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qos-entries = <8>;
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qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418
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@ -599,23 +601,23 @@
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<&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
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<&clock_mmss MMSS_CAMSS_AHB_CLK>,
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<&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
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<&clock_mmss VFE1_CLK_SRC>,
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<&clock_mmss MMSS_CAMSS_VFE1_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE1_STREAM_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE1_AHB_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>,
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<&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>,
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<&clock_mmss VFE1_CLK_SRC>,
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<&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>;
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clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
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"bimc_smmu_ahb_clk", "bimc_smmu_axi_clk",
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"camss_ahb_clk", "camss_top_ahb_clk",
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"camss_ahb_clk", "camss_top_ahb_clk", "vfe_clk_src",
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"camss_vfe_clk", "camss_vfe_stream_clk",
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"camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk",
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"camss_vfe_vbif_axi_clk", "vfe_clk_src",
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"camss_vfe_vbif_axi_clk",
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"camss_csi_vfe_clk";
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qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 404000000 0
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0 0 0 0 0 0 0 0 0 0 0 480000000 0
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0 0 0 0 0 0 0 0 0 0 0 576000000 0>;
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qcom,clock-rates = <0 0 0 0 0 0 404000000 0 0 0 0 0 0
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0 0 0 0 0 0 480000000 0 0 0 0 0 0
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0 0 0 0 0 0 576000000 0 0 0 0 0 0>;
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status = "ok";
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qos-entries = <8>;
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qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418
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