evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

pinctrl: Add mux options 3 and 4 for rockchip pinctrl

Browse source 
Newer Rockchip SoCs have more muxing slots.  Add slots 3 and 4 since
the rk3288 table goes all the way up to 4.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Doug Anderson 2014-08-08 15:29:09 -07:00 • committed by Linus Walleij
parent 4f671cb25e
commit f3ababa8ba
2 changed files with 5 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
View file

@ -2,8 +2,8 @@
The Rockchip Pinmux Controller, enables the IC The Rockchip Pinmux Controller, enables the IC
to share one PAD to several functional blocks. The sharing is done by to share one PAD to several functional blocks. The sharing is done by
multiplexing the PAD input/output signals. For each PAD there are up to multiplexing the PAD input/output signals. For each PAD there are several
4 muxing options with option 0 being the use as a GPIO. muxing options with option 0 being the use as a GPIO.
Please refer to pinctrl-bindings.txt in this directory for details of the Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the common pinctrl bindings used by client devices, including the meaning of the
@ -58,7 +58,7 @@ Deprecated properties for gpio sub nodes:
Required properties for pin configuration node: Required properties for pin configuration node:
- rockchip,pins: 3 integers array, represents a group of pins mux and config - rockchip,pins: 3 integers array, represents a group of pins mux and config
setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>. setting. The format is rockchip,pins = <PIN_BANK PIN_BANK_IDX MUX &phandle>.
The MUX 0 means gpio and MUX 1 to 3 mean the specific device function. The MUX 0 means gpio and MUX 1 to N mean the specific device function.
The phandle of a node containing the generic pinconfig options The phandle of a node containing the generic pinconfig options
to use, as described in pinctrl-bindings.txt in this directory. to use, as described in pinctrl-bindings.txt in this directory.

2
include/dt-bindings/pinctrl/rockchip.h
View file

@ -28,5 +28,7 @@
#define RK_FUNC_GPIO 0 #define RK_FUNC_GPIO 0
#define RK_FUNC_1 1 #define RK_FUNC_1 1
#define RK_FUNC_2 2 #define RK_FUNC_2 2
#define RK_FUNC_3 3
#define RK_FUNC_4 4
#endif #endif