arm64: Add options to disable I/D caches

Add the ability to individually disable the Instruction and
Data caches on ARM64 CPUs, by means of the SCTLR[I] and
SCTLR[C] bits. This may be useful for performance
profiling, as well as for troubleshooting potential cache
problems.

Change-Id: Ibd7fc796ddf6984c7f05dcd844432164e28bb021
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
[abhimany: resolve trivial merge conflicts]
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>

arch/arm64/Kconfig

@@ -456,6 +456,25 @@ config ARM64_16K_PAGES
 	  requires applications compiled with 16K (or a multiple of 16K)
 	  aligned segments.
 
+config ARM64_DCACHE_DISABLE
+	bool "Disable CPU Data Caches"
+	help
+	  Disable CPU data cache usage by setting the SCTLR[C] bit during
+	  kernel initialization. This will result in a considerable
+	  performance impact, but may be useful in certain situations.
+
+	  If you are not sure what to do, select 'N' here.
+
+config ARM64_ICACHE_DISABLE
+	bool "Disable CPU Instruction Caches"
+	help
+	  Disable CPU instruction cache usage by setting the SCTLR[I]
+	  bit during kernel initialization. This will result in a
+	  considerable performance impact, but may be useful in certain
+	  situations.
+
+	  If you are not sure what to do, select 'N' here.
+
 config ARM64_64K_PAGES
 	bool "64KB"
 	help

arch/arm64/mm/proc.S

@@ -273,5 +273,16 @@ ENDPROC(__cpu_setup)
 	 */
 	.type	crval, #object
 crval:
+#ifdef CONFIG_ARM64_ICACHE_DISABLE
+#define CR_IBIT		0
+#else
+#define CR_IBIT		0x1000
+#endif
+
+#ifdef CONFIG_ARM64_DCACHE_DISABLE
+#define CR_CBIT		0
+#else
+#define CR_CBIT		0x4
+#endif
 	.word	0xfcffffff			// clear
-	.word	0x34d5d91d			// set
+	.word	0x34d5d91d | CR_IBIT | CR_CBIT	// set