From 19740f9d535bdc41785b46dba450c1aa3ee69601 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Tue, 13 Dec 2016 15:39:20 +0530 Subject: [PATCH] soc: qcom: pil-q6v5: Update the reset sequence for qdspv62.1.2/1.5 Update the reset sequence to read each write while enabling QDSP6 memory bank one at a time. This will make sure whether write is complete or not. Also add logs during Mss shutdown, It will help to debug Mss restart and shutdown case. Change-Id: I9f2cb058a7e59b573fc64662ee7b5bff49b18ea7 Signed-off-by: Gaurav Kohli --- drivers/soc/qcom/pil-msa.c | 1 + drivers/soc/qcom/pil-q6v5.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/soc/qcom/pil-msa.c b/drivers/soc/qcom/pil-msa.c index 3c3ae693f615..01fc8bff1eca 100644 --- a/drivers/soc/qcom/pil-msa.c +++ b/drivers/soc/qcom/pil-msa.c @@ -278,6 +278,7 @@ int pil_mss_shutdown(struct pil_desc *pil) struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc); int ret = 0; + dev_info(pil->dev, "MSS is shutting down\n"); if (drv->axi_halt_base) { pil_q6v5_halt_axi_port(pil, drv->axi_halt_base + MSS_Q6_HALT_BASE); diff --git a/drivers/soc/qcom/pil-q6v5.c b/drivers/soc/qcom/pil-q6v5.c index a1cd3b1eeaff..6bafa46a5c0b 100644 --- a/drivers/soc/qcom/pil-q6v5.c +++ b/drivers/soc/qcom/pil-q6v5.c @@ -512,6 +512,8 @@ static int __pil_q6v55_reset(struct pil_desc *pil) val |= BIT(i); writel_relaxed(val, drv->reg_base + QDSP6V6SS_MEM_PWR_CTL); + val = readl_relaxed(drv->reg_base + + QDSP6V6SS_MEM_PWR_CTL); /* * Wait for 1us for both memory peripheral and * data array to turn on.