ixgbe: add new bus type for intergrated I/O interface (IOSF)
With this patch we add support for a new bus type ixgbe_bus_type_internal. X550em devices use IOSF and not PCIe bus so this new type is to accommodate them. Signed-off-by: Donald C Skidmore <donald.c.skidmore@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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3 changed files with 12 additions and 1 deletions
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@ -246,11 +246,19 @@ static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
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static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
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static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
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int expected_gts)
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int expected_gts)
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{
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{
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struct ixgbe_hw *hw = &adapter->hw;
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int max_gts = 0;
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int max_gts = 0;
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enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
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enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
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enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
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enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
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struct pci_dev *pdev;
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struct pci_dev *pdev;
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/* Some devices are not connected over PCIe and thus do not negotiate
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* speed. These devices do not have valid bus info, and thus any report
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* we generate may not be correct.
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*/
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if (hw->bus.type == ixgbe_bus_type_internal)
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return;
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/* determine whether to use the parent device */
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/* determine whether to use the parent device */
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if (ixgbe_pcie_from_parent(&adapter->hw))
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if (ixgbe_pcie_from_parent(&adapter->hw))
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pdev = adapter->pdev->bus->parent->self;
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pdev = adapter->pdev->bus->parent->self;
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@ -8837,9 +8845,10 @@ skip_sriov:
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hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
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hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
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/* pick up the PCI bus settings for reporting later */
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/* pick up the PCI bus settings for reporting later */
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hw->mac.ops.get_bus_info(hw);
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if (ixgbe_pcie_from_parent(hw))
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if (ixgbe_pcie_from_parent(hw))
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ixgbe_get_parent_bus_info(adapter);
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ixgbe_get_parent_bus_info(adapter);
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else
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hw->mac.ops.get_bus_info(hw);
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/* calculate the expected PCIe bandwidth required for optimal
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/* calculate the expected PCIe bandwidth required for optimal
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* performance. Note that some older parts will never have enough
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* performance. Note that some older parts will never have enough
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@ -3067,6 +3067,7 @@ enum ixgbe_bus_type {
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ixgbe_bus_type_pci,
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ixgbe_bus_type_pci,
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ixgbe_bus_type_pcix,
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ixgbe_bus_type_pcix,
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ixgbe_bus_type_pci_express,
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ixgbe_bus_type_pci_express,
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ixgbe_bus_type_internal,
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ixgbe_bus_type_reserved
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ixgbe_bus_type_reserved
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};
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};
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@ -620,6 +620,7 @@ static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
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**/
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**/
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static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
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static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
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{
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{
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hw->bus.type = ixgbe_bus_type_internal;
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hw->bus.width = ixgbe_bus_width_unknown;
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hw->bus.width = ixgbe_bus_width_unknown;
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hw->bus.speed = ixgbe_bus_speed_unknown;
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hw->bus.speed = ixgbe_bus_speed_unknown;
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