msm: mdss: Replace thulium with msm8996 in display code

Use appropriate SOC name. Also replace all
instances of thulia with kryo.

Change-Id: I3d21e3534fdf113190882c84ee5426ee929da131
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
[cip@codeaurora.org: Always build mdss_mdp_pp_v1_7.c]
Signed-off-by: Clarence Ip <cip@codeaurora.org>

Documentation/devicetree/bindings/fb/mdss-dsi-ctrl.txt

@@ -19,11 +19,11 @@ Required properties:
 					interface is mapped.
 - qcom,mdss-mdp:			pHandle that specifies the mdss-mdp device.
 - qcom,platform-regulator-settings:	An array of length 7 or 5 that specifies the PHY
-					regulator settings. It use 5 bytes for thulium pll.
+					regulator settings. It use 5 bytes for 8996 pll.
 - qcom,platform-strength-ctrl:		An array of length 2 or 10 that specifies the PHY
-					strengthCtrl settings. It use 10 bytes for thulium pll.
+					strengthCtrl settings. It use 10 bytes for 8996 pll.
 - qcom,platform-lane-config:		An array of length 45 or 20 that specifies the PHY
-					lane configuration settings. It use 20 bytes for thulium pll.
+					lane configuration settings. It use 20 bytes for 8996 pll.
 - qcom,dsi-pref-prim-pan:		phandle that specifies the primary panel to be used
 					with the controller.
 

Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt

@@ -37,7 +37,7 @@ Required properties:
 					"display_2" = DISPLAY_2
 - qcom,mdss-dsi-panel-timings:		An array of length 12 that specifies the PHY
 					timing settings for the panel.
-- qcom,mdss-dsi-panel-timings-thulium:		An array of length 40 char that specifies the thulium PHY lane
+- qcom,mdss-dsi-panel-timings-8996:		An array of length 40 char that specifies the 8996 PHY lane
 					timing settings for the panel.
 - qcom,mdss-dsi-on-command:		A byte stream formed by multiple dcs packets base on
 					qcom dsi controller protocol.
@@ -464,7 +464,7 @@ Example:
 		qcom,mdss-dsi-panel-clockrate = <424000000>;
 		qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33
 					22 27 1e 03 04 00];
-                qcom,mdss-dsi-panel-timings-thulium = [23 20 06 09 05 03 04 a0
+                qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0
                                 23 20 06 09 05 03 04 a0
                                 23 20 06 09 05 03 04 a0
                                 23 20 06 09 05 03 04 a0

drivers/video/fbdev/msm/Makefile

@@ -22,9 +22,7 @@ mdss-mdp-objs += mdss_mdp_wfd.o
 obj-$(CONFIG_FB_MSM_MDSS) += mdss-mdp.o
 obj-$(CONFIG_FB_MSM_MDSS) += mdss_mdp_debug.o
 
-ifeq ($(CONFIG_ARCH_MSMTHULIUM),y)
 mdss-mdp-objs += mdss_mdp_pp_v1_7.o
-endif
 
 ifeq ($(CONFIG_FB_MSM_MDSS),y)
 obj-$(CONFIG_DEBUG_FS) += mdss_debug.o mdss_debug_xlog.o

drivers/video/fbdev/msm/mdss_dsi.h

@@ -53,7 +53,7 @@
 #define MDSS_DSI_HW_REV_102		0x10020000	/* 8084    */
 #define MDSS_DSI_HW_REV_103		0x10030000	/* 8994    */
 #define MDSS_DSI_HW_REV_103_1		0x10030001	/* 8916/8936 */
-#define MDSS_DSI_HW_REV_104             0x10040000      /* thulium   */
+#define MDSS_DSI_HW_REV_104             0x10040000      /* 8996   */
 
 #define NONE_PANEL "none"
 

drivers/video/fbdev/msm/mdss_dsi_panel.c

@@ -1695,13 +1695,13 @@ static int mdss_panel_parse_dt(struct device_node *np,
 	for (i = 0; i < len; i++)
 		pinfo->mipi.dsi_phy_db.timing[i] = data[i];
 
-	data = of_get_property(np, "qcom,mdss-dsi-panel-timings-thulium", &len);
+	data = of_get_property(np, "qcom,mdss-dsi-panel-timings-8996", &len);
 	if ((!data) || (len != 40)) {
-		pr_debug("%s:%d, Unable to read thulium Phy lane timing settings",
+		pr_debug("%s:%d, Unable to read 8996 Phy lane timing settings",
 		       __func__, __LINE__);
 	} else {
 		for (i = 0; i < len; i++)
-			pinfo->mipi.dsi_phy_db.timing_thulium[i] = data[i];
+			pinfo->mipi.dsi_phy_db.timing_8996[i] = data[i];
 	}
 
 	pinfo->mipi.lp11_init = of_property_read_bool(np,

drivers/video/fbdev/msm/mdss_mdp_formats.h

@@ -174,14 +174,14 @@ enum {
 
 static struct mdss_fudge_factor ubwc_rt_factors[][UBWC_TOTAL_FORMATS] = {
 	/* RGB_565_UBWC	| RGBA_8888_UBWC | YUV_H2V2_UBWC */
-	{{1, 1} ,	 {126, 100} ,	  {123, 100} } , /* Thulium v0 */
-	{{1, 1} ,	 {126, 100} ,	  {123, 100} } , /* Thulium v1,v2 */
+	{{1, 1} ,	 {126, 100} ,	  {123, 100} } , /* 8996 v0 */
+	{{1, 1} ,	 {126, 100} ,	  {123, 100} } , /* 8996 v1,v2 */
 };
 
 static struct mdss_fudge_factor ubwc_nrt_factors[][UBWC_TOTAL_FORMATS] = {
 	/* RGB_565_UBWC	| RGBA_8888_UBWC | YUV_H2V2_UBWC */
-	{{1, 1} ,	 {146, 100} ,	 {1,   1} } ,	/* Thulium v0 */
-	{{1, 1} ,	 {146, 100} ,	 {128, 100} } ,	/* Thulium v1,v2 */
+	{{1, 1} ,	 {146, 100} ,	 {1,   1} } ,	/* 8996 v0 */
+	{{1, 1} ,	 {146, 100} ,	 {128, 100} } ,	/* 8996 v1,v2 */
 };
 
 /*

drivers/video/fbdev/msm/mdss_mdp_pp.h

@@ -160,15 +160,7 @@ struct mdss_pp_res_type {
 	void *pp_data_res;
 };
 
-#ifdef CONFIG_ARCH_MSMTHULIUM
 void *pp_get_driver_ops(struct mdp_pp_driver_ops *ops);
-#else
-static inline void *pp_get_driver_ops(struct mdp_pp_driver_ops *ops)
-{
-	memset(ops, 0, sizeof(struct mdp_pp_driver_ops));
-	return NULL;
-}
-#endif
 
 static inline void pp_sts_set_split_bits(u32 *sts, u32 bits)
 {

drivers/video/fbdev/msm/mdss_panel.h

@@ -228,16 +228,16 @@ struct lcd_panel_info {
 
 /* DSI PHY configuration */
 struct mdss_dsi_phy_ctrl {
-	char regulator[7];	/* thulium, 1 * 5 */
+	char regulator[7];	/* 8996, 1 * 5 */
 	char timing[12];
 	char ctrl[4];
-	char strength[10];	/* thulium, 2 * 5 */
+	char strength[10];	/* 8996, 2 * 5 */
 	char bistctrl[6];
 	uint32_t pll[21];
-	char lanecfg[45];	/* thulium, 4 * 5 */
+	char lanecfg[45];	/* 8996, 4 * 5 */
 	bool reg_ldo_mode;
 
-	char timing_thulium[40];/* thulium, 8 * 5 */
+	char timing_8996[40];/* 8996, 8 * 5 */
 	char regulator_len;
 	char strength_len;
 	char lanecfg_len;

drivers/video/fbdev/msm/msm_mdss_io_8974.c

@@ -40,9 +40,9 @@
 #define SW_RESET_PLL BIT(0)
 #define PWRDN_B BIT(7)
 
-/* thulium */
-#define DATALANE_OFFSET_FROM_BASE_THULIUM	0x100
-#define DATALANE_SIZE_THULIUM			0x80
+/* 8996 */
+#define DATALANE_OFFSET_FROM_BASE_8996	0x100
+#define DATALANE_SIZE_8996			0x80
 
 #define DSIPHY_CMN_GLBL_TEST_CTRL		0x0018
 #define DSIPHY_CMN_CTRL_0			0x001c
@@ -400,7 +400,7 @@ static void mdss_dsi_20nm_phy_config(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
 	MIPI_OUTP((ctrl_pdata->phy_io.base) + MDSS_DSI_DSIPHY_CTRL_0, 0x7f);
 }
 
-static void mdss_dsi_thulium_pll_source_standalone(
+static void mdss_dsi_8996_pll_source_standalone(
 				struct mdss_dsi_ctrl_pdata *ctrl)
 {
 	u32 data;
@@ -415,7 +415,7 @@ static void mdss_dsi_thulium_pll_source_standalone(
 	MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_CMN_GLBL_TEST_CTRL, data);
 }
 
-static void mdss_dsi_thulium_pll_source_from_right(
+static void mdss_dsi_8996_pll_source_from_right(
 				struct mdss_dsi_ctrl_pdata *ctrl)
 {
 	u32 data;
@@ -433,7 +433,7 @@ static void mdss_dsi_thulium_pll_source_from_right(
 	MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_PLL_PLL_BANDGAP, 0x3);
 }
 
-static void mdss_dsi_thulium_pll_source_from_left(
+static void mdss_dsi_8996_pll_source_from_left(
 				struct mdss_dsi_ctrl_pdata *ctrl)
 {
 	u32 data;
@@ -448,7 +448,7 @@ static void mdss_dsi_thulium_pll_source_from_left(
 	MIPI_OUTP((ctrl->phy_io.base) + DSIPHY_CMN_GLBL_TEST_CTRL, data);
 }
 
-static void mdss_dsi_thulium_phy_config(struct mdss_dsi_ctrl_pdata *ctrl)
+static void mdss_dsi_8996_phy_config(struct mdss_dsi_ctrl_pdata *ctrl)
 {
 	struct mdss_dsi_phy_ctrl *pd;
 	int j, off, ln, cnt, ln_off;
@@ -484,8 +484,8 @@ static void mdss_dsi_thulium_phy_config(struct mdss_dsi_ctrl_pdata *ctrl)
 		 * data lane size: 0x80
 		 */
 		base = ctrl->phy_io.base +
-				DATALANE_OFFSET_FROM_BASE_THULIUM;
-		base += (ln * DATALANE_SIZE_THULIUM); /* lane base */
+				DATALANE_OFFSET_FROM_BASE_8996;
+		base += (ln * DATALANE_SIZE_8996); /* lane base */
 
 		/* lane cfg, 4 * 5 */
 		cnt = 4;
@@ -503,7 +503,7 @@ static void mdss_dsi_thulium_phy_config(struct mdss_dsi_ctrl_pdata *ctrl)
 		/* phy timing, 8 * 5 */
 		cnt = 8;
 		ln_off = cnt * ln;
-		ip = &pd->timing_thulium[ln_off];
+		ip = &pd->timing_8996[ln_off];
 		off = 0x18;
 		for (j = 0; j < cnt; j++, off += 4)
 			MIPI_OUTP(base + off, *ip++);
@@ -534,11 +534,11 @@ static void mdss_dsi_thulium_phy_config(struct mdss_dsi_ctrl_pdata *ctrl)
 
 	if (mdss_dsi_split_display_enabled()) {
 		if (mdss_dsi_is_left_ctrl(ctrl))
-			mdss_dsi_thulium_pll_source_from_left(ctrl);
+			mdss_dsi_8996_pll_source_from_left(ctrl);
 		else
-			mdss_dsi_thulium_pll_source_from_right(ctrl);
+			mdss_dsi_8996_pll_source_from_right(ctrl);
 	} else {
-		mdss_dsi_thulium_pll_source_standalone(ctrl);
+		mdss_dsi_8996_pll_source_standalone(ctrl);
 	}
 
 	wmb(); /* make sure registers committed */
@@ -556,14 +556,14 @@ static void mdss_dsi_20nm_phy_init(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
 	mdss_dsi_20nm_phy_config(ctrl_pdata);
 }
 
-static void mdss_dsi_thulium_phy_init(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
+static void mdss_dsi_8996_phy_init(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
 {
 	if (!ctrl_pdata) {
 		pr_err("%s: Invalid input data\n", __func__);
 		return;
 	}
 
-	mdss_dsi_thulium_phy_config(ctrl_pdata);
+	mdss_dsi_8996_phy_config(ctrl_pdata);
 }
 
 static void mdss_dsi_phy_init(struct mdss_dsi_ctrl_pdata *ctrl)
@@ -575,7 +575,7 @@ static void mdss_dsi_phy_init(struct mdss_dsi_ctrl_pdata *ctrl)
 
 	switch (ctrl->hw_rev) {
 	case MDSS_DSI_HW_REV_104:
-		mdss_dsi_thulium_phy_init(ctrl);
+		mdss_dsi_8996_phy_init(ctrl);
 		break;
 	case MDSS_DSI_HW_REV_103:
 		mdss_dsi_20nm_phy_init(ctrl);

include/uapi/linux/msm_mdp.h

@@ -103,7 +103,9 @@
 #define MDSS_MDP_HW_REV_103_1	MDSS_MDP_REV(1, 3, 1) /* 8084 v1.1 */
 #define MDSS_MDP_HW_REV_105	MDSS_MDP_REV(1, 5, 0) /* 8994 v1.0 */
 #define MDSS_MDP_HW_REV_106	MDSS_MDP_REV(1, 6, 0) /* 8916 v1.0 */
-#define MDSS_MDP_HW_REV_107	MDSS_MDP_REV(1, 7, 0)
+#define MDSS_MDP_HW_REV_107	MDSS_MDP_REV(1, 7, 0) /* 8996 v1 */
+#define MDSS_MDP_HW_REV_107_1	MDSS_MDP_REV(1, 7, 1) /* 8996 v2 */
+#define MDSS_MDP_HW_REV_107_2	MDSS_MDP_REV(1, 7, 2) /* 8996 v3 */
 #define MDSS_MDP_HW_REV_108	MDSS_MDP_REV(1, 8, 0) /* 8939 v1.0 */
 #define MDSS_MDP_HW_REV_109	MDSS_MDP_REV(1, 9, 0) /* 8994 v2.0 */
 #define MDSS_MDP_HW_REV_110	MDSS_MDP_REV(1, 10, 0) /* 8992 v1.0 */