From f96e94247a5b3b1160feb85a23a7772494205b83 Mon Sep 17 00:00:00 2001 From: Padmanabhan Komanduru Date: Wed, 15 Nov 2017 18:51:05 +0530 Subject: [PATCH] clk: qcom: mdss: fix the divider programming for DisplayPort PLL Fix the divider programming of DisplayPort PLL with the correct value. Without this, display doesn't up fine with certain resolutions on some sinks when link rate is 5.4 GHz. Change-Id: I7c5a452a9df757240a1c6c3d371bd46a16f98efd Signed-off-by: Padmanabhan Komanduru --- drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c b/drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c index 0bd7e6413a6b..2d40fdeabcae 100644 --- a/drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c +++ b/drivers/clk/msm/mdss/mdss-dp-pll-8998-util.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -128,10 +128,10 @@ int vco_divided_clk_set_div(struct div_clk *clk, int div) auxclk_div = MDSS_PLL_REG_R(dp_res->phy_base, DP_PHY_VCO_DIV); auxclk_div &= ~0x03; /* bits 0 to 1 */ - auxclk_div |= 1; /* Default divider */ - if (div == 4) auxclk_div |= 2; + else + auxclk_div |= 1; /* Default divider */ MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_VCO_DIV, auxclk_div);