evie/android_kernel_oneplus_msm8998
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clk: qcom: add MDSS PLL support for msmfalcon

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Add the msmfalcon compatible string to MDSS PLL driver dt
table list so that MDSS PLL driver initialization takes place
for msmflacon platform.

Change-Id: I806456737485dfcbca8a71d59db0927bbd843708
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
This commit is contained in:
Sandeep Panda 2016-12-20 11:58:47 +05:30 • committed by Vishnuvardhan Prodduturi
parent e379f786aa
commit f9bf3dd7e9
3 changed files with 7 additions and 1 deletions
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2
Documentation/devicetree/bindings/fb/mdss-pll.txt
View file

@ -15,7 +15,7 @@ Required properties:
"qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2", "qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2",
"qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8", "qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8",
"qcom,mdss_dsi_pll_8998", "qcom,mdss_dp_pll_8998", "qcom,mdss_dsi_pll_8998", "qcom,mdss_dp_pll_8998",
"qcom,mdss_hdmi_pll_8998" "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dsi_pll_msmfalcon"
- cell-index: Specifies the controller used - cell-index: Specifies the controller used
- reg: offset and length of the register set for the device. - reg: offset and length of the register set for the device.
- reg-names : names to refer to register sets related to this device - reg-names : names to refer to register sets related to this device

5
drivers/clk/qcom/mdss/mdss-pll.c
View file

@ -133,6 +133,10 @@ static int mdss_pll_resource_parse(struct platform_device *pdev,
pll_res->pll_interface_type = MDSS_DSI_PLL_8996; pll_res->pll_interface_type = MDSS_DSI_PLL_8996;
pll_res->target_id = MDSS_PLL_TARGET_8996; pll_res->target_id = MDSS_PLL_TARGET_8996;
pll_res->revision = 2; pll_res->revision = 2;
} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_msmfalcon")) {
pll_res->pll_interface_type = MDSS_DSI_PLL_8996;
pll_res->target_id = MDSS_PLL_TARGET_MSMFALCON;
pll_res->revision = 2;
} else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8998")) { } else if (!strcmp(compatible_stream, "qcom,mdss_dsi_pll_8998")) {
pll_res->pll_interface_type = MDSS_DSI_PLL_8998; pll_res->pll_interface_type = MDSS_DSI_PLL_8998;
} else if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_8998")) { } else if (!strcmp(compatible_stream, "qcom,mdss_dp_pll_8998")) {
@ -378,6 +382,7 @@ static const struct of_device_id mdss_pll_dt_match[] = {
{.compatible = "qcom,mdss_hdmi_pll_8996_v3_1p8"}, {.compatible = "qcom,mdss_hdmi_pll_8996_v3_1p8"},
{.compatible = "qcom,mdss_dp_pll_8998"}, {.compatible = "qcom,mdss_dp_pll_8998"},
{.compatible = "qcom,mdss_hdmi_pll_8998"}, {.compatible = "qcom,mdss_hdmi_pll_8998"},
{.compatible = "qcom,mdss_dsi_pll_msmfalcon"},
{} {}
}; };

1
drivers/clk/qcom/mdss/mdss-pll.h
View file

@ -51,6 +51,7 @@ enum {
enum { enum {
MDSS_PLL_TARGET_8996, MDSS_PLL_TARGET_8996,
MDSS_PLL_TARGET_MSMFALCON,
}; };
#define DFPS_MAX_NUM_OF_FRAME_RATES 20 #define DFPS_MAX_NUM_OF_FRAME_RATES 20