Staging: rtl8187se: r8185b_init.c: Fix some spacing issues
Fix some more spacing issues I missed before Signed-off-by: Andrew Miller <amiller@amilx.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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3d2ec48ee4
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1 changed files with 21 additions and 23 deletions
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@ -71,10 +71,10 @@ static u8 MAC_REG_TABLE[][2] = {
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/* PAGA 0: */
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/* PAGA 0: */
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{0x5e, 0x00}, {0x9f, 0x03}
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{0x5e, 0x00}, {0x9f, 0x03}
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};
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};
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static u8 ZEBRA_AGC[] = {
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static u8 ZEBRA_AGC[] = {
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0,
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0,
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0x7E, 0x7E, 0x7E, 0x7E, 0x7D, 0x7C, 0x7B, 0x7A, 0x79, 0x78, 0x77, 0x76, 0x75, 0x74, 0x73, 0x72,
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0x7E, 0x7E, 0x7E, 0x7E, 0x7D, 0x7C, 0x7B, 0x7A, 0x79, 0x78, 0x77, 0x76, 0x75, 0x74, 0x73, 0x72,
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0x71, 0x70, 0x6F, 0x6E, 0x6D, 0x6C, 0x6B, 0x6A, 0x69, 0x68, 0x67, 0x66, 0x65, 0x64, 0x63, 0x62,
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0x71, 0x70, 0x6F, 0x6E, 0x6D, 0x6C, 0x6B, 0x6A, 0x69, 0x68, 0x67, 0x66, 0x65, 0x64, 0x63, 0x62,
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@ -94,7 +94,7 @@ static u32 ZEBRA_RF_RX_GAIN_TABLE[] = {
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0x0183, 0x0163, 0x0143, 0x0123, 0x0103
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0x0183, 0x0163, 0x0143, 0x0123, 0x0103
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};
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};
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static u8 OFDM_CONFIG[] = {
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static u8 OFDM_CONFIG[] = {
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/* OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX */
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/* OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX */
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/* OFDM reg0x3C[4]=1'b1: Enable RX power saving mode */
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/* OFDM reg0x3C[4]=1'b1: Enable RX power saving mode */
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/* ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test */
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/* ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test */
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@ -121,22 +121,20 @@ void PlatformIOWrite1Byte(struct net_device *dev, u32 offset, u8 data)
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{
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{
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write_nic_byte(dev, offset, data);
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write_nic_byte(dev, offset, data);
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read_nic_byte(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
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read_nic_byte(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
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}
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}
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void PlatformIOWrite2Byte(struct net_device *dev, u32 offset, u16 data)
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void PlatformIOWrite2Byte(struct net_device *dev, u32 offset, u16 data)
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{
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{
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write_nic_word(dev, offset, data);
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write_nic_word(dev, offset, data);
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read_nic_word(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
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read_nic_word(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
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}
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}
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u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
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u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
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void PlatformIOWrite4Byte(struct net_device *dev, u32 offset, u32 data)
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void PlatformIOWrite4Byte(struct net_device *dev, u32 offset, u32 data)
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{
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{
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/* {by amy 080312 */
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/* {by amy 080312 */
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if (offset == PhyAddr) {
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if (offset == PhyAddr) {
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/* For Base Band configuration. */
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/* For Base Band configuration. */
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unsigned char cmdByte;
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unsigned char cmdByte;
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unsigned long dataBytes;
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unsigned long dataBytes;
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@ -156,7 +154,7 @@ void PlatformIOWrite4Byte(struct net_device *dev, u32 offset, u32 data)
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*/
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*/
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/* NdisAcquireSpinLock( &(pDevice->IoSpinLock) ); */
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/* NdisAcquireSpinLock( &(pDevice->IoSpinLock) ); */
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for (idx = 0; idx < 30; idx++) {
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for (idx = 0; idx < 30; idx++) {
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/* Make sure command bit is clear before access it. */
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/* Make sure command bit is clear before access it. */
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u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
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u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
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if ((u1bTmp & BIT7) == 0)
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if ((u1bTmp & BIT7) == 0)
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@ -224,9 +222,9 @@ static int HwHSSIThreeWire(struct net_device *dev,
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u8 TryCnt;
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u8 TryCnt;
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u8 u1bTmp;
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u8 u1bTmp;
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do {
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do {
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/* Check if WE and RE are cleared. */
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/* Check if WE and RE are cleared. */
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for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) {
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for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) {
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u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
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u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
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if ((u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0)
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if ((u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0)
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break;
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break;
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@ -252,7 +250,7 @@ static int HwHSSIThreeWire(struct net_device *dev,
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write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
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write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
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if (bSI) {
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if (bSI) {
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/* jong: HW SI read must set reg84[3]=0. */
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/* jong: HW SI read must set reg84[3]=0. */
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u1bTmp = read_nic_byte(dev, RFPinsSelect);
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u1bTmp = read_nic_byte(dev, RFPinsSelect);
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u1bTmp &= ~BIT3;
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u1bTmp &= ~BIT3;
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@ -260,14 +258,14 @@ static int HwHSSIThreeWire(struct net_device *dev,
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}
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}
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/* Fill up data buffer for write operation. */
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/* Fill up data buffer for write operation. */
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if (bWrite) {
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if (bWrite) {
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if (nDataBufBitCnt == 16) {
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if (nDataBufBitCnt == 16) {
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write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
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write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
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} else if (nDataBufBitCnt == 64) {
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} else if (nDataBufBitCnt == 64) {
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/* RTL8187S shouldn't enter this case */
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/* RTL8187S shouldn't enter this case */
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write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
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write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
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write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
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write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
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} else {
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} else {
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int idx;
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int idx;
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int ByteCnt = nDataBufBitCnt / 8;
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int ByteCnt = nDataBufBitCnt / 8;
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/* printk("%d\n",nDataBufBitCnt); */
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/* printk("%d\n",nDataBufBitCnt); */
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@ -293,11 +291,11 @@ static int HwHSSIThreeWire(struct net_device *dev,
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write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
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write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
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}
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}
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} else { /* read */
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} else { /* read */
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if (bSI) {
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if (bSI) {
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/* SI - reg274[3:0] : RF register's Address */
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/* SI - reg274[3:0] : RF register's Address */
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write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
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write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
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} else {
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} else {
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/* PI - reg274[15:12] : RF register's Address */
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/* PI - reg274[15:12] : RF register's Address */
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write_nic_word(dev, SW_3W_DB0, (*((u16 *)pDataBuf)) << 12);
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write_nic_word(dev, SW_3W_DB0, (*((u16 *)pDataBuf)) << 12);
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}
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}
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@ -323,11 +321,11 @@ static int HwHSSIThreeWire(struct net_device *dev,
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write_nic_byte(dev, SW_3W_CMD1, 0);
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write_nic_byte(dev, SW_3W_CMD1, 0);
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/* Read back data for read operation. */
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/* Read back data for read operation. */
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if (bWrite == 0) {
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if (bWrite == 0) {
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if (bSI) {
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if (bSI) {
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/* Serial Interface : reg363_362[11:0] */
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/* Serial Interface : reg363_362[11:0] */
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*((u16 *)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
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*((u16 *)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
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} else {
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} else {
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/* Parallel Interface : reg361_360[11:0] */
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/* Parallel Interface : reg361_360[11:0] */
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*((u16 *)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
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*((u16 *)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
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}
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}
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@ -335,7 +333,7 @@ static int HwHSSIThreeWire(struct net_device *dev,
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*((u16 *)pDataBuf) &= 0x0FFF;
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*((u16 *)pDataBuf) &= 0x0FFF;
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}
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}
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} while (0);
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} while (0);
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return bResult;
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return bResult;
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}
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}
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@ -1296,7 +1294,7 @@ bool MgntActSet_RF_State(struct net_device *dev, RT_RF_POWER_STATE StateToSet, u
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Prevent the race condition of RF state change. By Bruce, 2007-11-28.
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Prevent the race condition of RF state change. By Bruce, 2007-11-28.
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Only one thread can change the RF state at one time, and others should wait to be executed.
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Only one thread can change the RF state at one time, and others should wait to be executed.
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*/
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*/
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while (true) {
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while (true) {
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spin_lock_irqsave(&priv->rf_ps_lock, flag);
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spin_lock_irqsave(&priv->rf_ps_lock, flag);
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if (priv->RFChangeInProgress) {
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if (priv->RFChangeInProgress) {
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spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
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spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
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