ath10k: define an enum to enable cycle counter wraparound logic
QCA988X hw implements a different cycle counter wraparound behaviour when compared to QCA4019. To properly handle different wraparound logic for these chipsets replace already available bool hw_params member, has_shifted_cc_wraparound, with an enum which could be extended to handle different wraparound behaviour. This patch keeps the existing logic functionally same and a prepares cycle counter wraparound handling to extend for other chips. Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com> [kvalo@qca.qualcomm.com: change also QCA9887 wrap type] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
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4 changed files with 20 additions and 9 deletions
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@ -56,7 +56,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.name = "qca988x hw2.0",
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.name = "qca988x hw2.0",
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.patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
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.uart_pin = 7,
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.uart_pin = 7,
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.has_shifted_cc_wraparound = true,
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.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
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.otp_exe_param = 0,
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.otp_exe_param = 0,
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.channel_counters_freq_hz = 88000,
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.channel_counters_freq_hz = 88000,
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.max_probe_resp_desc_thres = 0,
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.max_probe_resp_desc_thres = 0,
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@ -75,7 +75,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.name = "qca9887 hw1.0",
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.name = "qca9887 hw1.0",
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.patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR,
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.uart_pin = 7,
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.uart_pin = 7,
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.has_shifted_cc_wraparound = true,
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.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
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.otp_exe_param = 0,
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.otp_exe_param = 0,
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.channel_counters_freq_hz = 88000,
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.channel_counters_freq_hz = 88000,
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.max_probe_resp_desc_thres = 0,
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.max_probe_resp_desc_thres = 0,
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@ -246,7 +246,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
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.name = "qca4019 hw1.0",
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.name = "qca4019 hw1.0",
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.patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
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.patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
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.uart_pin = 7,
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.uart_pin = 7,
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.has_shifted_cc_wraparound = true,
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.cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL,
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.otp_exe_param = 0x0010000,
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.otp_exe_param = 0x0010000,
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.continuous_frag_desc = true,
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.continuous_frag_desc = true,
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.cck_rate_map_rev2 = true,
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.cck_rate_map_rev2 = true,
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@ -713,12 +713,10 @@ struct ath10k {
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int uart_pin;
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int uart_pin;
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u32 otp_exe_param;
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u32 otp_exe_param;
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/* This is true if given HW chip has a quirky Cycle Counter
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/* Type of hw cycle counter wraparound logic, for more info
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* wraparound which resets to 0x7fffffff instead of 0. All
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* refer enum ath10k_hw_cc_wraparound_type.
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* other CC related counters (e.g. Rx Clear Count) are divided
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* by 2 so they never wraparound themselves.
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*/
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*/
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bool has_shifted_cc_wraparound;
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enum ath10k_hw_cc_wraparound_type cc_wraparound_type;
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/* Some of chip expects fragment descriptor to be continuous
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/* Some of chip expects fragment descriptor to be continuous
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* memory for any TX operation. Set continuous_frag_desc flag
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* memory for any TX operation. Set continuous_frag_desc flag
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@ -179,11 +179,13 @@ void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
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u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
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u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
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{
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{
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u32 cc_fix = 0;
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u32 cc_fix = 0;
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enum ath10k_hw_cc_wraparound_type wraparound_type;
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survey->filled |= SURVEY_INFO_TIME |
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survey->filled |= SURVEY_INFO_TIME |
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SURVEY_INFO_TIME_BUSY;
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SURVEY_INFO_TIME_BUSY;
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if (ar->hw_params.has_shifted_cc_wraparound && cc < cc_prev) {
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wraparound_type = ar->hw_params.cc_wraparound_type;
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if (wraparound_type == ATH10K_HW_CC_WRAP_SHIFTED_ALL && cc < cc_prev) {
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cc_fix = 0x7fffffff;
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cc_fix = 0x7fffffff;
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survey->filled &= ~SURVEY_INFO_TIME_BUSY;
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survey->filled &= ~SURVEY_INFO_TIME_BUSY;
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}
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}
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@ -351,6 +351,17 @@ enum ath10k_hw_4addr_pad {
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ATH10K_HW_4ADDR_PAD_BEFORE,
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ATH10K_HW_4ADDR_PAD_BEFORE,
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};
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};
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enum ath10k_hw_cc_wraparound_type {
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ATH10K_HW_CC_WRAP_DISABLED = 0,
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/* This type is when the HW chip has a quirky Cycle Counter
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* wraparound which resets to 0x7fffffff instead of 0. All
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* other CC related counters (e.g. Rx Clear Count) are divided
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* by 2 so they never wraparound themselves.
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*/
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ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1,
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};
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/* Target specific defines for MAIN firmware */
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/* Target specific defines for MAIN firmware */
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#define TARGET_NUM_VDEVS 8
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#define TARGET_NUM_VDEVS 8
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#define TARGET_NUM_PEER_AST 2
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#define TARGET_NUM_PEER_AST 2
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