evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

ARM: dts: msm: Add support for clock debug for MSMfalcon/MSMtriton

Browse source 
Clock debug mux node is required for global clock controller, CPU, graphics
clock controller and multimedia clock controller. Add syscon device nodes
for the required nodes.

Change-Id: Ie6571c7b780f184e6af78c3c339e51820a09dfa8
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This commit is contained in:
Taniya Das 2016-12-08 16:53:50 +05:30
parent 050365a312
commit fa4531b69a
4 changed files with 70 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
arch/arm/boot/dts/qcom/msmfalcon-rumi.dts
View file

@ -137,3 +137,8 @@
vccq2-max-microamp = <600000>;
qcom,disable-lpm;
};
&clock_debug {
compatible = "qcom,dummycc";
clock-output-names = "debug_clocks";
};

31
arch/arm/boot/dts/qcom/msmfalcon.dtsi
View file

@ -884,7 +884,7 @@
};
clock_gcc: clock-controller@100000 {
compatible = "qcom,gcc-msmfalcon";
compatible = "qcom,gcc-msmfalcon", "syscon";
reg = <0x100000 0x94000>;
vdd_dig-supply = <&pm2falcon_s3_level>;
vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>;
@ -922,6 +922,35 @@
#reset-cells = <1>;
};
cpu_debug: syscon@1791101c {
compatible = "syscon";
reg = <0x1791101c 0x4>;
};
gpu_debug: syscon@05065120 {
compatible = "syscon";
reg = <0x05065120 0x4>;
};
mmss_debug: syscon@c8c0900 {
compatible = "syscon";
reg = <0xc8c0900 0x4>;
};
clock_debug: qcom,cc-debug@62000 {
compatible = "qcom,gcc-debug-msmfalcon";
reg = <0x62000 0x4>;
reg-names = "dbg_offset";
clocks = <&clock_rpmcc RPM_XO_CLK_SRC>;
clock-names = "xo_clk_src";
qcom,cc-count = <4>;
qcom,gcc = <&clock_gcc>;
qcom,cpu = <&cpu_debug>;
qcom,mmss = <&mmss_debug>;
qcom,gpu = <&gpu_debug>;
#clock-cells = <1>;
};
sdhc_1: sdhci@c0c4000 {
compatible = "qcom,sdhci-msm-v5";
reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>;

5
arch/arm/boot/dts/qcom/msmtriton-rumi.dts
View file

@ -75,3 +75,8 @@
compatible = "qcom,dummycc";
clock-output-names = "mmss_clocks";
};
&clock_debug {
compatible = "qcom,dummycc";
clock-output-names = "debug_clocks";
};

31
arch/arm/boot/dts/qcom/msmtriton.dtsi
View file

@ -561,7 +561,7 @@
};
clock_gcc: clock-controller@100000 {
compatible = "qcom,gcc-msmfalcon";
compatible = "qcom,gcc-msmfalcon", "syscon";
reg = <0x100000 0x94000>;
vdd_dig-supply = <&pm2falcon_s3_level>;
vdd_dig_ao-supply = <&pm2falcon_s3_level_ao>;
@ -599,6 +599,35 @@
#reset-cells = <1>;
};
cpu_debug: syscon@1791101c {
compatible = "syscon";
reg = <0x1791101c 0x4>;
};
gpu_debug: syscon@05065120 {
compatible = "syscon";
reg = <0x05065120 0x4>;
};
mmss_debug: syscon@c8c0900 {
compatible = "syscon";
reg = <0xc8c0900 0x4>;
};
clock_debug: qcom,cc-debug@62000 {
compatible = "qcom,gcc-debug-msmfalcon";
reg = <0x62000 0x4>;
reg-names = "dbg_offset";
clocks = <&clock_rpmcc RPM_XO_CLK_SRC>;
clock-names = "xo_clk_src";
qcom,cc-count = <4>;
qcom,gcc = <&clock_gcc>;
qcom,cpu = <&cpu_debug>;
qcom,mmss = <&mmss_debug>;
qcom,gpu = <&gpu_debug>;
#clock-cells = <1>;
};
qcom,ipc-spinlock@1f40000 {
compatible = "qcom,ipc-spinlock-sfpb";
reg = <0x1f40000 0x8000>;