msm: mdss: avoid missing ECG due to thread preemption

On smart panels, Early Clock Gating (ECG), is initiated when current
frame transfer is finished and no new frame update is queued. To track
these two different states, driver maintains the state machine
for HW transfer and SW's new frame update. Currently SW state machine is
cleared only after HW transfer has started. Now in normal scenarios SW
state should be cleared before HW is finished and if there is no new
frame update queued then ECG will be initiated. However due to CPU
scheduling, thread that needs to clear SW state got preempted. In the
meantime HW finished the transfer and updated its state machine in the
interrupt context. Since at this moment SW state wasn't cleared, ECG
was not initiated. Avoid this situation by clearing SW state before HW
transfer is started.

CRs-fixed: 941832
Change-Id: I44828c6077eb8729162127b521f4fd4add2e3bcb
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
This commit is contained in:
Ujwal Patel 2015-11-20 11:28:18 -08:00 committed by David Keitel
parent 830723857d
commit fa52907f13

View file

@ -1890,6 +1890,13 @@ static int mdss_mdp_cmd_kickoff(struct mdss_mdp_ctl *ctl, void *arg)
sctx->current_pp_num);
}
mdss_mdp_ctl_perf_set_transaction_status(ctl,
PERF_SW_COMMIT_STATE, PERF_STATUS_DONE);
if (sctl) {
mdss_mdp_ctl_perf_set_transaction_status(sctl,
PERF_SW_COMMIT_STATE, PERF_STATUS_DONE);
}
if (!ctx->autorefresh_pending_frame_cnt && !ctl->cmd_autorefresh_en) {
/* Kickoff */
mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_START, 1);
@ -1899,14 +1906,6 @@ static int mdss_mdp_cmd_kickoff(struct mdss_mdp_ctl *ctl, void *arg)
ctx->autorefresh_pending_frame_cnt);
}
mdss_mdp_ctl_perf_set_transaction_status(ctl,
PERF_SW_COMMIT_STATE, PERF_STATUS_DONE);
if (sctl) {
mdss_mdp_ctl_perf_set_transaction_status(sctl,
PERF_SW_COMMIT_STATE, PERF_STATUS_DONE);
}
mb();
MDSS_XLOG(ctl->num, ctx->current_pp_num,
sctx ? sctx->current_pp_num : -1, atomic_read(&ctx->koff_cnt));