iwlwifi: pcie: move the ICT / non-ICT handling functions
The purpose of this is to be able to call these functions from the interrupt handler and not from the primary interrupt handler. Reviewed-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
This commit is contained in:
Emmanuel Grumbach
parent
85bf9da193
commit
fc84472b8d
1 changed files with 162 additions and 162 deletions
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@ -807,6 +807,168 @@ static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
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wake_up(&trans_pcie->wait_command_queue);
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wake_up(&trans_pcie->wait_command_queue);
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}
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}
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/* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
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static irqreturn_t iwl_pcie_isr_non_ict(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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u32 inta;
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lockdep_assert_held(&trans_pcie->irq_lock);
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trace_iwlwifi_dev_irq(trans->dev);
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/* Discover which interrupts are active/pending */
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inta = iwl_read32(trans, CSR_INT);
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if (inta & (~trans_pcie->inta_mask)) {
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IWL_DEBUG_ISR(trans,
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"We got a masked interrupt (0x%08x)...Ack and ignore\n",
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inta & (~trans_pcie->inta_mask));
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iwl_write32(trans, CSR_INT, inta & (~trans_pcie->inta_mask));
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inta &= trans_pcie->inta_mask;
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}
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/* Ignore interrupt if there's nothing in NIC to service.
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* This may be due to IRQ shared with another device,
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* or due to sporadic interrupts thrown from our NIC. */
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if (!inta) {
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IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
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/*
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* Re-enable interrupts here since we don't have anything to
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* service, but only in case the handler won't run. Note that
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* the handler can be scheduled because of a previous
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* interrupt.
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*/
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if (test_bit(STATUS_INT_ENABLED, &trans->status) &&
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!trans_pcie->inta)
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iwl_enable_interrupts(trans);
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return IRQ_NONE;
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}
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if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
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/* Hardware disappeared. It might have already raised
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* an interrupt */
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IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
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return IRQ_HANDLED;
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}
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if (iwl_have_debug_level(IWL_DL_ISR))
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IWL_DEBUG_ISR(trans,
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"ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
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inta, trans_pcie->inta_mask,
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iwl_read32(trans, CSR_FH_INT_STATUS));
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trans_pcie->inta |= inta;
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/* the thread will service interrupts and re-enable them */
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return IRQ_WAKE_THREAD;
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}
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/* a device (PCI-E) page is 4096 bytes long */
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#define ICT_SHIFT 12
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#define ICT_SIZE (1 << ICT_SHIFT)
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#define ICT_COUNT (ICT_SIZE / sizeof(u32))
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/* interrupt handler using ict table, with this interrupt driver will
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* stop using INTA register to get device's interrupt, reading this register
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* is expensive, device will write interrupts in ICT dram table, increment
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* index then will fire interrupt to driver, driver will OR all ICT table
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* entries from current index up to table entry with 0 value. the result is
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* the interrupt we need to service, driver will set the entries back to 0 and
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* set index.
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*/
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static irqreturn_t iwl_pcie_isr_ict(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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unsigned long flags;
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irqreturn_t ret;
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u32 inta;
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u32 val = 0;
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u32 read;
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spin_lock_irqsave(&trans_pcie->irq_lock, flags);
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/* dram interrupt table not set yet,
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* use legacy interrupt.
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*/
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if (unlikely(!trans_pcie->use_ict)) {
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ret = iwl_pcie_isr_non_ict(trans);
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spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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return ret;
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}
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trace_iwlwifi_dev_irq(trans->dev);
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/* Ignore interrupt if there's nothing in NIC to service.
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* This may be due to IRQ shared with another device,
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* or due to sporadic interrupts thrown from our NIC. */
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read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
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trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
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if (!read) {
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IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
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goto none;
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}
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/*
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* Collect all entries up to the first 0, starting from ict_index;
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* note we already read at ict_index.
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*/
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do {
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val |= read;
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IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
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trans_pcie->ict_index, read);
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trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
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trans_pcie->ict_index =
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iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
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read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
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trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
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read);
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} while (read);
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/* We should not get this value, just ignore it. */
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if (val == 0xffffffff)
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val = 0;
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/*
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* this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
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* (bit 15 before shifting it to 31) to clear when using interrupt
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* coalescing. fortunately, bits 18 and 19 stay set when this happens
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* so we use them to decide on the real state of the Rx bit.
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* In order words, bit 15 is set if bit 18 or bit 19 are set.
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*/
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if (val & 0xC0000)
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val |= 0x8000;
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inta = (0xff & val) | ((0xff00 & val) << 16);
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IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled(sw) 0x%08x ict 0x%08x\n",
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inta, trans_pcie->inta_mask, val);
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if (iwl_have_debug_level(IWL_DL_ISR))
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IWL_DEBUG_ISR(trans, "enabled(hw) 0x%08x\n",
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iwl_read32(trans, CSR_INT_MASK));
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inta &= trans_pcie->inta_mask;
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trans_pcie->inta |= inta;
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/* iwl_pcie_tasklet() will service interrupts and re-enable them */
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if (likely(inta)) {
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spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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return IRQ_WAKE_THREAD;
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}
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ret = IRQ_HANDLED;
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none:
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/* re-enable interrupts here since we don't have anything to service.
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* only Re-enable if disabled by irq.
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*/
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if (test_bit(STATUS_INT_ENABLED, &trans->status) &&
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!trans_pcie->inta)
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iwl_enable_interrupts(trans);
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spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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return ret;
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}
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irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
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irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
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{
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{
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struct iwl_trans *trans = dev_id;
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struct iwl_trans *trans = dev_id;
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@ -1019,11 +1181,6 @@ out:
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*
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*
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******************************************************************************/
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******************************************************************************/
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/* a device (PCI-E) page is 4096 bytes long */
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#define ICT_SHIFT 12
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#define ICT_SIZE (1 << ICT_SHIFT)
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#define ICT_COUNT (ICT_SIZE / sizeof(u32))
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/* Free dram table */
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/* Free dram table */
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void iwl_pcie_free_ict(struct iwl_trans *trans)
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void iwl_pcie_free_ict(struct iwl_trans *trans)
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{
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{
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@ -1110,163 +1267,6 @@ void iwl_pcie_disable_ict(struct iwl_trans *trans)
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spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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}
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}
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/* legacy (non-ICT) ISR. Assumes that trans_pcie->irq_lock is held */
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static irqreturn_t iwl_pcie_isr_non_ict(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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u32 inta;
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lockdep_assert_held(&trans_pcie->irq_lock);
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trace_iwlwifi_dev_irq(trans->dev);
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/* Discover which interrupts are active/pending */
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inta = iwl_read32(trans, CSR_INT);
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if (inta & (~trans_pcie->inta_mask)) {
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IWL_DEBUG_ISR(trans,
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"We got a masked interrupt (0x%08x)...Ack and ignore\n",
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inta & (~trans_pcie->inta_mask));
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iwl_write32(trans, CSR_INT, inta & (~trans_pcie->inta_mask));
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inta &= trans_pcie->inta_mask;
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}
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/* Ignore interrupt if there's nothing in NIC to service.
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* This may be due to IRQ shared with another device,
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* or due to sporadic interrupts thrown from our NIC. */
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if (!inta) {
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IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
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/*
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* Re-enable interrupts here since we don't have anything to
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* service, but only in case the handler won't run. Note that
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* the handler can be scheduled because of a previous
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* interrupt.
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*/
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if (test_bit(STATUS_INT_ENABLED, &trans->status) &&
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!trans_pcie->inta)
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iwl_enable_interrupts(trans);
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return IRQ_NONE;
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}
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if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
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/* Hardware disappeared. It might have already raised
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* an interrupt */
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IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
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return IRQ_HANDLED;
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}
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if (iwl_have_debug_level(IWL_DL_ISR))
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IWL_DEBUG_ISR(trans,
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"ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
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inta, trans_pcie->inta_mask,
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iwl_read32(trans, CSR_FH_INT_STATUS));
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trans_pcie->inta |= inta;
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/* the thread will service interrupts and re-enable them */
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return IRQ_WAKE_THREAD;
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}
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/* interrupt handler using ict table, with this interrupt driver will
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* stop using INTA register to get device's interrupt, reading this register
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* is expensive, device will write interrupts in ICT dram table, increment
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* index then will fire interrupt to driver, driver will OR all ICT table
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* entries from current index up to table entry with 0 value. the result is
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* the interrupt we need to service, driver will set the entries back to 0 and
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* set index.
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*/
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static irqreturn_t iwl_pcie_isr_ict(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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unsigned long flags;
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irqreturn_t ret;
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u32 inta;
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u32 val = 0;
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u32 read;
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spin_lock_irqsave(&trans_pcie->irq_lock, flags);
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/* dram interrupt table not set yet,
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* use legacy interrupt.
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*/
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if (unlikely(!trans_pcie->use_ict)) {
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ret = iwl_pcie_isr_non_ict(trans);
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spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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return ret;
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}
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trace_iwlwifi_dev_irq(trans->dev);
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/* Ignore interrupt if there's nothing in NIC to service.
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* This may be due to IRQ shared with another device,
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* or due to sporadic interrupts thrown from our NIC. */
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read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
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trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
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if (!read) {
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IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
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goto none;
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}
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/*
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* Collect all entries up to the first 0, starting from ict_index;
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* note we already read at ict_index.
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*/
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do {
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val |= read;
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IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
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trans_pcie->ict_index, read);
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trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
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trans_pcie->ict_index =
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iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
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read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
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trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
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read);
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} while (read);
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/* We should not get this value, just ignore it. */
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if (val == 0xffffffff)
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val = 0;
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/*
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* this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
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* (bit 15 before shifting it to 31) to clear when using interrupt
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* coalescing. fortunately, bits 18 and 19 stay set when this happens
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* so we use them to decide on the real state of the Rx bit.
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* In order words, bit 15 is set if bit 18 or bit 19 are set.
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*/
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if (val & 0xC0000)
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val |= 0x8000;
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inta = (0xff & val) | ((0xff00 & val) << 16);
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IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled(sw) 0x%08x ict 0x%08x\n",
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inta, trans_pcie->inta_mask, val);
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if (iwl_have_debug_level(IWL_DL_ISR))
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IWL_DEBUG_ISR(trans, "enabled(hw) 0x%08x\n",
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iwl_read32(trans, CSR_INT_MASK));
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inta &= trans_pcie->inta_mask;
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trans_pcie->inta |= inta;
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/* iwl_pcie_tasklet() will service interrupts and re-enable them */
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if (likely(inta)) {
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spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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return IRQ_WAKE_THREAD;
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}
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ret = IRQ_HANDLED;
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none:
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/* re-enable interrupts here since we don't have anything to service.
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* only Re-enable if disabled by irq.
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*/
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if (test_bit(STATUS_INT_ENABLED, &trans->status) &&
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!trans_pcie->inta)
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iwl_enable_interrupts(trans);
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spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
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return ret;
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}
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irqreturn_t iwl_pcie_isr(int irq, void *data)
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irqreturn_t iwl_pcie_isr(int irq, void *data)
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||||||
{
|
{
|
||||||
struct iwl_trans *trans = data;
|
struct iwl_trans *trans = data;
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue