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MIPS: EMMA2RH: Remove emma2rh_gpio_irq_base

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Let's use immediate value, instead.  This also saves memory footprint,
and probably a little bit faster.

Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Shinya Kuribayashi 2008-10-24 01:32:11 +09:00 • committed by Ralf Baechle
parent 68ed1ca912
commit fcb3cfe7f0
2 changed files with 10 additions and 13 deletions
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4
arch/mips/emma/markeins/irq.c
View file

@ -54,7 +54,7 @@
*/ */
extern void emma2rh_sw_irq_init(void); extern void emma2rh_sw_irq_init(void);
extern void emma2rh_gpio_irq_init(u32 base); extern void emma2rh_gpio_irq_init(void);
extern void emma2rh_irq_init(void); extern void emma2rh_irq_init(void);
extern void emma2rh_irq_dispatch(void); extern void emma2rh_irq_dispatch(void);
@ -104,7 +104,7 @@ void __init arch_init_irq(void)
/* init all controllers */ /* init all controllers */
emma2rh_irq_init(); emma2rh_irq_init();
emma2rh_sw_irq_init(); emma2rh_sw_irq_init();
emma2rh_gpio_irq_init(EMMA2RH_GPIO_IRQ_BASE); emma2rh_gpio_irq_init();
mips_cpu_irq_init(); mips_cpu_irq_init();
/* setup cascade interrupts */ /* setup cascade interrupts */

19
arch/mips/emma/markeins/irq_markeins.c
View file

@ -30,8 +30,6 @@
#include <asm/debug.h> #include <asm/debug.h>
#include <asm/emma/emma2rh.h> #include <asm/emma/emma2rh.h>
static int emma2rh_gpio_irq_base = -1;
void ll_emma2rh_sw_irq_enable(int reg); void ll_emma2rh_sw_irq_enable(int reg);
void ll_emma2rh_sw_irq_disable(int reg); void ll_emma2rh_sw_irq_disable(int reg);
void ll_emma2rh_gpio_irq_enable(int reg); void ll_emma2rh_gpio_irq_enable(int reg);
@ -91,17 +89,17 @@ void ll_emma2rh_sw_irq_disable(int irq)
static void emma2rh_gpio_irq_enable(unsigned int irq) static void emma2rh_gpio_irq_enable(unsigned int irq)
{ {
ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base); ll_emma2rh_gpio_irq_enable(irq - EMMA2RH_GPIO_IRQ_BASE);
} }
static void emma2rh_gpio_irq_disable(unsigned int irq) static void emma2rh_gpio_irq_disable(unsigned int irq)
{ {
ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base); ll_emma2rh_gpio_irq_disable(irq - EMMA2RH_GPIO_IRQ_BASE);
} }
static void emma2rh_gpio_irq_ack(unsigned int irq) static void emma2rh_gpio_irq_ack(unsigned int irq)
{ {
irq -= emma2rh_gpio_irq_base; irq -= EMMA2RH_GPIO_IRQ_BASE;
emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq));
ll_emma2rh_gpio_irq_disable(irq); ll_emma2rh_gpio_irq_disable(irq);
} }
@ -109,7 +107,7 @@ static void emma2rh_gpio_irq_ack(unsigned int irq)
static void emma2rh_gpio_irq_end(unsigned int irq) static void emma2rh_gpio_irq_end(unsigned int irq)
{ {
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
ll_emma2rh_gpio_irq_enable(irq - emma2rh_gpio_irq_base); ll_emma2rh_gpio_irq_enable(irq - EMMA2RH_GPIO_IRQ_BASE);
} }
struct irq_chip emma2rh_gpio_irq_controller = { struct irq_chip emma2rh_gpio_irq_controller = {
@ -121,14 +119,13 @@ struct irq_chip emma2rh_gpio_irq_controller = {
.end = emma2rh_gpio_irq_end, .end = emma2rh_gpio_irq_end,
}; };
void emma2rh_gpio_irq_init(u32 irq_base) void emma2rh_gpio_irq_init(void)
{ {
u32 i; u32 i;
for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++) for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
set_irq_chip(i, &emma2rh_gpio_irq_controller); set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i,
&emma2rh_gpio_irq_controller);
emma2rh_gpio_irq_base = irq_base;
} }
void ll_emma2rh_gpio_irq_enable(int irq) void ll_emma2rh_gpio_irq_enable(int irq)