From fd85b29d717a381b3125b91c82a8c5692d1ce7c1 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Fri, 19 Sep 2014 15:00:41 -0700 Subject: [PATCH] msm: pcie: add PCIe support for thulium Add PCIe support for thulium. Added enumeration, interrupts, and hardware configurations support for PCIe. Change-Id: I48b2fc8a51303a6aea7b1b2a97c4de25f19ded4c Signed-off-by: Tony Truong --- .../devicetree/bindings/pci/msm_pcie.txt | 6 + drivers/pci/host/pci-msm.c | 986 ++++++++++-------- 2 files changed, 577 insertions(+), 415 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/msm_pcie.txt b/Documentation/devicetree/bindings/pci/msm_pcie.txt index 10cf6c54649b..c4d21f825ce4 100644 --- a/Documentation/devicetree/bindings/pci/msm_pcie.txt +++ b/Documentation/devicetree/bindings/pci/msm_pcie.txt @@ -10,6 +10,8 @@ Required properties: - reg-names: indicates various resources passed to driver by name. Should be "parf", "phy", "dm_core", "elbi", "conf", "io", "bars". These correspond to different modules within the PCIe core. + - ranges: For details of ranges properties, please refer to: + "Documentation\devicetree\bindings\pci\pci.txt" - interrupts: Should be in the format <0 1 2> and it is an index to the interrupt-map that contains PCIe related interrupts. - #interrupt-cells: Should provide a value of 1. @@ -66,6 +68,7 @@ Optional Properties: - qcom,msi-gicm-addr: MSI address for GICv2m. - qcom,msi-gicm-base: MSI IRQ base for GICv2m. - qcom,ext-ref-clk: The reference clock is external. + - qcom,common-phy: There is a common phy for all the Root Complexes. - qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become stable after power on, before de-assert the PERST to the endpoint. - qcom,tlp-rd-size: The max TLP read size (Calculation: 128 times 2 to the @@ -96,6 +99,8 @@ Example: <0xff300000 0xd00000>; reg-names = "parf", "dm_core", "elbi", "conf", "io", "bars"; + ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, + <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; interrupt-parent = <&pcie0>; interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12>; #interrupt-cells = <1>; @@ -157,6 +162,7 @@ Example: qcom,msi-gicm-base = <0x160>; qcom,ext-ref-clk; qcom,tlp-rd-size = <0x5>; + qcom,common-phy; qcom,ep-latency = <100>; qcom,msm-bus,name = "pcie0"; diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index 4a53e7eb5a30..50dc3e3e0c9e 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -44,124 +44,105 @@ #include #include +#define TX_BASE 0x1000 +#define RX_BASE 0x1200 +#define PCS_BASE 0x1400 -#define QSERDES_COM_PLL_VCOTAIL_EN 0x004 -#define QSERDES_COM_IE_TRIM 0x00C -#define QSERDES_COM_IP_TRIM 0x010 -#define QSERDES_COM_PLL_CNTRL 0x014 -#define QSERDES_COM_PLL_IP_SETI 0x024 -#define QSERDES_COM_PLL_CP_SETI 0x034 -#define QSERDES_COM_PLL_IP_SETP 0x038 -#define QSERDES_COM_PLL_CP_SETP 0x03C -#define QSERDES_COM_ATB_SEL2 0x044 -#define QSERDES_COM_SYSCLK_EN_SEL_TXBAND 0x048 -#define QSERDES_COM_RESETSM_CNTRL 0x04C -#define QSERDES_COM_RESETSM_CNTRL2 0x050 -#define QSERDES_COM_PLLLOCK_CMP1 0x090 -#define QSERDES_COM_PLLLOCK_CMP2 0x094 -#define QSERDES_COM_PLLLOCK_CMP_EN 0x09C -#define QSERDES_COM_DEC_START1 0x0AC -#define QSERDES_COM_RES_CODE_START_SEG1 0x0E0 -#define QSERDES_COM_RES_CODE_CAL_CSR 0x0E8 -#define QSERDES_COM_RES_TRIM_CONTROL 0x0F0 -#define QSERDES_COM_DIV_FRAC_START1 0x100 -#define QSERDES_COM_DIV_FRAC_START2 0x104 -#define QSERDES_COM_DIV_FRAC_START3 0x108 -#define QSERDES_COM_DEC_START2 0x10C -#define QSERDES_COM_PLL_RXTXEPCLK_EN 0x110 -#define QSERDES_COM_PLL_CRCTRL 0x114 +#define TX(n, m) (TX_BASE + n * m * 0x1000) +#define RX(n, m) (RX_BASE + n * m * 0x1000) +#define PCS_PORT(n, m) (PCS_BASE + n * m * 0x1000) -#define QSERDES_COM_PLL_VCO_HIGH 0x14C -#define QSERDES_COM_RESET_SM 0x150 -#define QSERDES_COM_MUXVAL 0x154 -#define QSERDES_COM_CORE_RES_CODE_DN 0x158 -#define QSERDES_COM_CORE_RES_CODE_UP 0x15C -#define QSERDES_COM_CORE_VCO_TUNE 0x160 -#define QSERDES_COM_CORE_VCO_TAIL 0x164 -#define QSERDES_COM_CORE_KVCO_CODE 0x168 +#define QSERDES_COM_BG_TIMER 0x00C +#define QSERDES_COM_SSC_EN_CENTER 0x010 +#define QSERDES_COM_SSC_ADJ_PER1 0x014 +#define QSERDES_COM_SSC_ADJ_PER2 0x018 +#define QSERDES_COM_SSC_PER1 0x01C +#define QSERDES_COM_SSC_PER2 0x020 +#define QSERDES_COM_SSC_STEP_SIZE1 0x024 +#define QSERDES_COM_SSC_STEP_SIZE2 0x028 +#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 +#define QSERDES_COM_CLK_ENABLE1 0x038 +#define QSERDES_COM_SYS_CLK_CTRL 0x03C +#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 +#define QSERDES_COM_PLL_IVCO 0x048 +#define QSERDES_COM_LOCK_CMP1_MODE0 0x04C +#define QSERDES_COM_LOCK_CMP2_MODE0 0x050 +#define QSERDES_COM_LOCK_CMP3_MODE0 0x054 +#define QSERDES_COM_BG_TRIM 0x070 +#define QSERDES_COM_CLK_EP_DIV 0x074 +#define QSERDES_COM_CP_CTRL_MODE0 0x078 +#define QSERDES_COM_PLL_RCTRL_MODE0 0x084 +#define QSERDES_COM_PLL_CCTRL_MODE0 0x090 +#define QSERDES_COM_SYSCLK_EN_SEL 0x0AC +#define QSERDES_COM_RESETSM_CNTRL 0x0B4 +#define QSERDES_COM_RESTRIM_CTRL 0x0BC +#define QSERDES_COM_RESCODE_DIV_NUM 0x0C4 +#define QSERDES_COM_LOCK_CMP_EN 0x0C8 +#define QSERDES_COM_DEC_START_MODE0 0x0D0 +#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0DC +#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0E0 +#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0E4 +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10C +#define QSERDES_COM_VCO_TUNE_CTRL 0x124 +#define QSERDES_COM_VCO_TUNE_MAP 0x128 +#define QSERDES_COM_VCO_TUNE1_MODE0 0x12C +#define QSERDES_COM_VCO_TUNE2_MODE0 0x130 +#define QSERDES_COM_VCO_TUNE_TIMER1 0x144 +#define QSERDES_COM_VCO_TUNE_TIMER2 0x148 +#define QSERDES_COM_BG_CTRL 0x170 +#define QSERDES_COM_CLK_SELECT 0x174 +#define QSERDES_COM_HSCLK_SEL 0x178 +#define QSERDES_COM_CORECLK_DIV 0x184 +#define QSERDES_COM_CORE_CLK_EN 0x18C +#define QSERDES_COM_CMN_CONFIG 0x194 +#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19C +#define QSERDES_COM_DEBUG_BUS0 0x1A0 +#define QSERDES_COM_DEBUG_BUS1 0x1A4 +#define QSERDES_COM_DEBUG_BUS2 0x1A8 +#define QSERDES_COM_DEBUG_BUS3 0x1AC +#define QSERDES_COM_DEBUG_BUS_SEL 0x1B0 -#define QSERDES_RX_CDR_CONTROL1 0x400 -#define QSERDES_RX_CDR_CONTROL_HALF 0x408 -#define QSERDES_RX_UCDR_FO_GAIN 0x414 -#define QSERDES_RX_UCDR_SO_GAIN 0x418 -#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x41C -#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x4A8 -#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x4AC -#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x4B0 -#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x4B4 -#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x4BC -#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x4F0 -#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x4F4 -#define QSERDES_RX_SIGDET_ENABLES 0x4F8 -#define QSERDES_RX_SIGDET_CNTRL 0x500 -#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x504 +#define QSERDES_TX_N_DEBUG_BUS_SEL(n, m) (TX(n, m) + 0x64) +#define QSERDES_TX_N_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN(n, m) (TX(n, m) + 0x68) +#define QSERDES_TX_N_LANE_MODE(n, m) (TX(n, m) + 0x94) -#define QSERDES_RX_PI_CTRL1 0x558 -#define QSERDES_RX_PI_CTRL2 0x55C -#define QSERDES_RX_PI_QUAD 0x560 -#define QSERDES_RX_IDATA1 0x564 -#define QSERDES_RX_IDATA2 0x568 -#define QSERDES_RX_AUX_DATA1 0x56C -#define QSERDES_RX_AUX_DATA2 0x570 -#define QSERDES_RX_AC_JTAG_OUTP 0x574 -#define QSERDES_RX_AC_JTAG_OUTN 0x578 -#define QSERDES_RX_RX_SIGDET 0x57C -#define QSERDES_RX_RX_VDCOFF 0x580 -#define QSERDES_RX_IDAC_CAL_ON 0x584 -#define QSERDES_RX_IDAC_STATUS_I 0x588 -#define QSERDES_RX_IDAC_STATUS_Q 0x58C -#define QSERDES_RX_IDAC_STATUS_A 0x590 -#define QSERDES_RX_CALST_STATUS_I 0x594 -#define QSERDES_RX_CALST_STATUS_Q 0x598 -#define QSERDES_RX_CALST_STATUS_A 0x59C -#define QSERDES_RX_EOM_STATUS0 0x5A0 -#define QSERDES_RX_EOM_STATUS1 0x5A4 -#define QSERDES_RX_EOM_STATUS2 0x5A8 -#define QSERDES_RX_EOM_STATUS3 0x5AC -#define QSERDES_RX_EOM_STATUS4 0x5B0 -#define QSERDES_RX_EOM_STATUS5 0x5B4 -#define QSERDES_RX_EOM_STATUS6 0x5B8 -#define QSERDES_RX_EOM_STATUS7 0x5BC -#define QSERDES_RX_EOM_STATUS8 0x5C0 -#define QSERDES_RX_EOM_STATUS9 0x5C4 -#define QSERDES_RX_RX_ALOG_INTF_OBSV 0x5C8 -#define QSERDES_RX_READ_EQCODE 0x5CC -#define QSERDES_RX_READ_OFFSETCODE 0x5D0 +#define QSERDES_RX_N_UCDR_SO_GAIN(n, m) (RX(n, m) + 0x01C) +#define QSERDES_RX_N_UCDR_SO_SATURATION_AND_ENABLE(n, m) (RX(n, m) + 0x048) +#define QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL2(n, m) (RX(n, m) + 0x0D8) +#define QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL3(n, m) (RX(n, m) + 0x0DC) +#define QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL4(n, m) (RX(n, m) + 0x0E0) +#define QSERDES_RX_N_SIGDET_ENABLES(n, m) (RX(n, m) + 0x110) +#define QSERDES_RX_N_SIGDET_DEGLITCH_CNTRL(n, m) (RX(n, m) + 0x11C) +#define QSERDES_RX_N_SIGDET_LVL(n, m) (RX(n, m) + 0x118) -#define QSERDES_TX_RCV_DETECT_LVL 0x268 - -#define QSERDES_TX_BYP_EN_OUT 0x228 -#define QSERDES_TX_BIST_STATUS 0x2B4 -#define QSERDES_TX_BIST_ERROR_COUNT1 0x2B8 -#define QSERDES_TX_BIST_ERROR_COUNT2 0x2BC -#define QSERDES_TX_TX_ALOG_INTF_OBSV 0x2C0 -#define QSERDES_TX_PWM_DEC_STATUS 0x2C4 - -#define PCIE_PHY_SW_RESET 0x600 -#define PCIE_PHY_POWER_DOWN_CONTROL 0x604 -#define PCIE_PHY_START 0x608 -#define PCIE_PHY_ENDPOINT_REFCLK_DRIVE 0x648 -#define PCIE_PHY_RX_IDLE_DTCT_CNTRL 0x64C -#define PCIE_PHY_POWER_STATE_CONFIG1 0x650 -#define PCIE_PHY_POWER_STATE_CONFIG2 0x654 - -#define PCIE_PHY_TEST_CONTROL 0x6E8 - -#define PCIE_PHY_BIST_CHK_ERR_CNT_L 0x718 -#define PCIE_PHY_BIST_CHK_ERR_CNT_H 0x71C -#define PCIE_PHY_BIST_CHK_STATUS 0x720 -#define PCIE_PHY_LFPS_RXTERM_IRQ_SOURCE 0x724 -#define PCIE_PHY_PCS_STATUS 0x728 -#define PCIE_PHY_PCS_STATUS2 0x72C -#define PCIE_PHY_REVISION_ID0 0x730 -#define PCIE_PHY_REVISION_ID1 0x734 -#define PCIE_PHY_REVISION_ID2 0x738 -#define PCIE_PHY_REVISION_ID3 0x73C -#define PCIE_PHY_DEBUG_BUS_0_STATUS 0x740 -#define PCIE_PHY_DEBUG_BUS_1_STATUS 0x744 -#define PCIE_PHY_DEBUG_BUS_2_STATUS 0x748 -#define PCIE_PHY_DEBUG_BUS_3_STATUS 0x74C +#define PCIE_N_SW_RESET(n, m) (PCS_PORT(n, m) + 0x00) +#define PCIE_N_POWER_DOWN_CONTROL(n, m) (PCS_PORT(n, m) + 0x04) +#define PCIE_N_START_CONTROL(n, m) (PCS_PORT(n, m) + 0x08) +#define PCIE_N_ENDPOINT_REFCLK_DRIVE(n, m) (PCS_PORT(n, m) + 0x54) +#define PCIE_N_POWER_STATE_CONFIG1(n, m) (PCS_PORT(n, m) + 0x60) +#define PCIE_N_POWER_STATE_CONFIG4(n, m) (PCS_PORT(n, m) + 0x6C) +#define PCIE_N_TEST_CONTROL4(n, m) (PCS_PORT(n, m) + 0x11C) +#define PCIE_N_TEST_CONTROL5(n, m) (PCS_PORT(n, m) + 0x120) +#define PCIE_N_TEST_CONTROL6(n, m) (PCS_PORT(n, m) + 0x124) +#define PCIE_N_TEST_CONTROL7(n, m) (PCS_PORT(n, m) + 0x128) +#define PCIE_N_DEBUG_BUS_0_STATUS(n, m) (PCS_PORT(n, m) + 0x198) +#define PCIE_N_DEBUG_BUS_1_STATUS(n, m) (PCS_PORT(n, m) + 0x19C) +#define PCIE_N_DEBUG_BUS_2_STATUS(n, m) (PCS_PORT(n, m) + 0x1A0) +#define PCIE_N_DEBUG_BUS_3_STATUS(n, m) (PCS_PORT(n, m) + 0x1A4) +#define PCIE_COM_SW_RESET 0x400 +#define PCIE_COM_POWER_DOWN_CONTROL 0x404 +#define PCIE_COM_START_CONTROL 0x408 +#define PCIE_COM_DEBUG_BUS_BYTE0_INDEX 0x438 +#define PCIE_COM_DEBUG_BUS_BYTE1_INDEX 0x43C +#define PCIE_COM_DEBUG_BUS_BYTE2_INDEX 0x440 +#define PCIE_COM_DEBUG_BUS_BYTE3_INDEX 0x444 +#define PCIE_COM_PCS_READY_STATUS 0x448 +#define PCIE_COM_DEBUG_BUS_0_STATUS 0x45C +#define PCIE_COM_DEBUG_BUS_1_STATUS 0x460 +#define PCIE_COM_DEBUG_BUS_2_STATUS 0x464 +#define PCIE_COM_DEBUG_BUS_3_STATUS 0x468 #define PCIE20_PARF_SYS_CTRL 0x00 #define PCIE20_PARF_PM_STTS 0x24 @@ -173,6 +154,7 @@ #define PCIE20_PARF_TEST_BUS 0xE4 #define PCIE20_PARF_DBI_BASE_ADDR 0x168 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C +#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178 #define PCIE20_PARF_LTSSM 0x1B0 @@ -220,11 +202,7 @@ #define PCIE20_AER_ERR_SRC_ID_REG 0x134 #define PCIE_VENDOR_ID_RCP 0x17cb -#ifdef CONFIG_ARCH_MDM9640 -#define PCIE_DEVICE_ID_RCP 0x0301 -#else -#define PCIE_DEVICE_ID_RCP 0x0300 -#endif +#define PCIE_DEVICE_ID_RCP 0x0104 #define RD 0 #define WR 1 @@ -252,9 +230,9 @@ #define MAX_PROP_SIZE 32 #define MAX_RC_NAME_LEN 15 #define MSM_PCIE_MAX_VREG 3 -#define MSM_PCIE_MAX_CLK 7 +#define MSM_PCIE_MAX_CLK 13 #define MSM_PCIE_MAX_PIPE_CLK 1 -#define MAX_RC_NUM 2 +#define MAX_RC_NUM 3 #define MAX_DEVICE_NUM 20 #define PCIE_TLP_RD_SIZE 0x5 #define PCIE_MSI_NR_IRQS 256 @@ -292,7 +270,7 @@ ((bus << 24) | (devfn << 16)) #define PCIE_BUS_PRIV_DATA(pdev) \ - (((struct pci_sys_data *)pdev->bus->sysdata)->private_data) + (struct msm_pcie_dev_t *)(pdev->bus->sysdata) #define PCIE_GEN_DBG(x...) do { \ if (msm_pcie_debug_mask) \ @@ -444,6 +422,7 @@ struct msm_pcie_dev_t { struct platform_device *pdev; struct pci_dev *dev; struct regulator *gdsc; + struct regulator *gdsc_smmu; struct msm_pcie_vreg_info_t vreg[MSM_PCIE_MAX_VREG]; struct msm_pcie_gpio_info_t gpio[MSM_PCIE_MAX_GPIO]; struct msm_pcie_clk_info_t clk[MSM_PCIE_MAX_CLK]; @@ -498,6 +477,7 @@ struct msm_pcie_dev_t { bool aux_clk_sync; uint32_t n_fts; bool ext_ref_clk; + bool common_phy; uint32_t ep_latency; uint32_t current_bdf; uint32_t tlp_rd_size; @@ -557,6 +537,9 @@ static u32 wr_mask; static u32 wr_value; static ulong corr_counter_limit = 5; +/* counter to keep track if common PHY needs to be configured */ +static u32 num_rc_on; + /* Table to track info of PCIe devices */ static struct msm_pcie_device_info msm_pcie_dev_tbl[MAX_RC_NUM * MAX_DEVICE_NUM]; @@ -593,6 +576,12 @@ static struct msm_pcie_clk_info_t {NULL, "pcie_0_mstr_axi_clk", 0, true}, {NULL, "pcie_0_slv_axi_clk", 0, true}, {NULL, "pcie_0_ldo", 0, true}, + {NULL, "pcie_0_smmu_clk", 0, false}, + {NULL, "pcie_phy_cfg_ahb_clk", 0, false}, + {NULL, "pcie_phy_aux_clk", 0, false}, + {NULL, "pcie_phy_reset", 0, false}, + {NULL, "pcie_phy_com_reset", 0, false}, + {NULL, "pcie_phy_nocsr_com_phy_reset", 0, false}, {NULL, "pcie_0_phy_reset", 0, true} }, { @@ -602,7 +591,28 @@ static struct msm_pcie_clk_info_t {NULL, "pcie_1_mstr_axi_clk", 0, true}, {NULL, "pcie_1_slv_axi_clk", 0, true}, {NULL, "pcie_1_ldo", 0, true}, + {NULL, "pcie_1_smmu_clk", 0, false}, + {NULL, "pcie_phy_cfg_ahb_clk", 0, false}, + {NULL, "pcie_phy_aux_clk", 0, false}, + {NULL, "pcie_phy_reset", 0, false}, + {NULL, "pcie_phy_com_reset", 0, false}, + {NULL, "pcie_phy_nocsr_com_phy_reset", 0, false}, {NULL, "pcie_1_phy_reset", 0, true} + }, + { + {NULL, "pcie_2_ref_clk_src", 0, false}, + {NULL, "pcie_2_aux_clk", 1010000, true}, + {NULL, "pcie_2_cfg_ahb_clk", 0, true}, + {NULL, "pcie_2_mstr_axi_clk", 0, true}, + {NULL, "pcie_2_slv_axi_clk", 0, true}, + {NULL, "pcie_2_ldo", 0, true}, + {NULL, "pcie_2_smmu_clk", 0, false}, + {NULL, "pcie_phy_cfg_ahb_clk", 0, false}, + {NULL, "pcie_phy_aux_clk", 0, false}, + {NULL, "pcie_phy_reset", 0, false}, + {NULL, "pcie_phy_com_reset", 0, false}, + {NULL, "pcie_phy_nocsr_com_phy_reset", 0, false}, + {NULL, "pcie_2_phy_reset", 0, true} } }; @@ -614,6 +624,9 @@ static struct msm_pcie_clk_info_t }, { {NULL, "pcie_1_pipe_clk", 125000000, true}, + }, + { + {NULL, "pcie_2_pipe_clk", 125000000, true}, } }; @@ -784,167 +797,244 @@ static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev) static void pcie_phy_dump(struct msm_pcie_dev_t *dev) { int i, size; - int control_offset[6] = {0x60, 0x70, 0x80, 0xA0, 0xB0, 0xB0}; + u32 write_val; PCIE_DUMP(dev, "PCIe: RC%d PHY testbus\n", dev->rc_idx); - for (i = 0; i < 6; i++) { - switch (i) { - case 3: - msm_pcie_write_reg(dev->phy, - QSERDES_COM_ATB_SEL2, - 0x10); - break; - case 4: - msm_pcie_write_reg(dev->phy, - QSERDES_TX_BYP_EN_OUT, - 0x10); - break; - case 5: - msm_pcie_write_reg(dev->phy, - QSERDES_TX_BYP_EN_OUT, - 0x30); - break; - default: - break; - } - + for (i = 0; i < 12; i += 4) { + write_val = 0x18 + i; msm_pcie_write_reg(dev->phy, - PCIE_PHY_TEST_CONTROL, - control_offset[i]); + PCIE_N_TEST_CONTROL4(dev->rc_idx, dev->common_phy), + write_val); + + write_val++; + msm_pcie_write_reg(dev->phy, + PCIE_N_TEST_CONTROL5(dev->rc_idx, dev->common_phy), + write_val); + + write_val++; + msm_pcie_write_reg(dev->phy, + PCIE_N_TEST_CONTROL6(dev->rc_idx, dev->common_phy), + write_val); + + write_val++; + msm_pcie_write_reg(dev->phy, + PCIE_N_TEST_CONTROL7(dev->rc_idx, dev->common_phy), + write_val); PCIE_DUMP(dev, - "PCIe: RC%d PCIE_PHY_TEST_CONTROL: 0x%x\n", + "PCIe: RC%d PCIE_N_TEST_CONTROL4: 0x%x\n", dev->rc_idx, - readl_relaxed(dev->phy + PCIE_PHY_TEST_CONTROL)); + readl_relaxed(dev->phy + + PCIE_N_TEST_CONTROL4(dev->rc_idx, + dev->common_phy))); + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_N_TEST_CONTROL5: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_N_TEST_CONTROL5(dev->rc_idx, + dev->common_phy))); + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_N_TEST_CONTROL6: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_N_TEST_CONTROL6(dev->rc_idx, + dev->common_phy))); + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_N_TEST_CONTROL7: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_N_TEST_CONTROL7(dev->rc_idx, + dev->common_phy))); PCIE_DUMP(dev, "PCIe: RC%d PCIE_PHY_DEBUG_BUS_0_STATUS: 0x%x\n", dev->rc_idx, - readl_relaxed(dev->phy + PCIE_PHY_DEBUG_BUS_0_STATUS)); + readl_relaxed(dev->phy + + PCIE_N_DEBUG_BUS_0_STATUS(dev->rc_idx, + dev->common_phy))); PCIE_DUMP(dev, - "PCIe: RC%d PCIE_PHY_DEBUG_BUS_1_STATUS: 0x%x\n", + "PCIe: RC%d PCIE_N_DEBUG_BUS_1_STATUS: 0x%x\n", dev->rc_idx, - readl_relaxed(dev->phy + PCIE_PHY_DEBUG_BUS_1_STATUS)); + readl_relaxed(dev->phy + + PCIE_N_DEBUG_BUS_1_STATUS(dev->rc_idx, + dev->common_phy))); PCIE_DUMP(dev, - "PCIe: RC%d PCIE_PHY_DEBUG_BUS_2_STATUS: 0x%x\n", + "PCIe: RC%d PCIE_N_DEBUG_BUS_2_STATUS: 0x%x\n", dev->rc_idx, - readl_relaxed(dev->phy + PCIE_PHY_DEBUG_BUS_2_STATUS)); + readl_relaxed(dev->phy + + PCIE_N_DEBUG_BUS_2_STATUS(dev->rc_idx, + dev->common_phy))); PCIE_DUMP(dev, - "PCIe: RC%d PCIE_PHY_DEBUG_BUS_3_STATUS: 0x%x\n", + "PCIe: RC%d PCIE_N_DEBUG_BUS_3_STATUS: 0x%x\n\n", dev->rc_idx, - readl_relaxed(dev->phy + PCIE_PHY_DEBUG_BUS_3_STATUS)); + readl_relaxed(dev->phy + + PCIE_N_DEBUG_BUS_3_STATUS(dev->rc_idx, + dev->common_phy))); } - PCIE_DUMP(dev, "PCIe: RC%d PHY register dump\n", dev->rc_idx); + for (i = 0; i < 2; i++) { + write_val = 0x2 + i; - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_COM_PLL_VCO_HIGH: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_COM_PLL_VCO_HIGH)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_COM_RESET_SM: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_COM_RESET_SM)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_COM_MUXVAL: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_COM_MUXVAL)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_COM_CORE_RES_CODE_DN: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_COM_CORE_RES_CODE_DN)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_COM_CORE_RES_CODE_UP: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_COM_CORE_RES_CODE_UP)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_COM_CORE_VCO_TUNE: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_COM_CORE_VCO_TUNE)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_COM_CORE_VCO_TAIL: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_COM_CORE_VCO_TAIL)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_COM_CORE_KVCO_CODE: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_COM_CORE_KVCO_CODE)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_PI_CTRL1: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_PI_CTRL1)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_PI_CTRL2: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_PI_CTRL2)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_PI_QUAD: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_PI_QUAD)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_IDATA1: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_IDATA1)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_IDATA2: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_IDATA2)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_AUX_DATA1: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_AUX_DATA1)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_AUX_DATA2: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_AUX_DATA2)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_AC_JTAG_OUTP: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_AC_JTAG_OUTP)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_AC_JTAG_OUTN: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_AC_JTAG_OUTN)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_RX_SIGDET: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_RX_SIGDET)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_RX_VDCOFF: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_RX_VDCOFF)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_IDAC_CAL_ON: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_IDAC_CAL_ON)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_IDAC_STATUS_I: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_IDAC_STATUS_I)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_IDAC_STATUS_Q: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_IDAC_STATUS_Q)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_IDAC_STATUS_A: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_IDAC_STATUS_A)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_CALST_STATUS_I: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_CALST_STATUS_I)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_CALST_STATUS_Q: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_CALST_STATUS_Q)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_CALST_STATUS_A: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_CALST_STATUS_A)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_EOM_STATUS0: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_EOM_STATUS0)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_EOM_STATUS1: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_EOM_STATUS1)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_EOM_STATUS2: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_EOM_STATUS2)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_EOM_STATUS3: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_EOM_STATUS3)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_EOM_STATUS4: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_EOM_STATUS4)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_EOM_STATUS5: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_EOM_STATUS5)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_EOM_STATUS6: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_EOM_STATUS6)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_EOM_STATUS7: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_EOM_STATUS7)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_EOM_STATUS8: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_EOM_STATUS8)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_EOM_STATUS9: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_EOM_STATUS9)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_RX_ALOG_INTF_OBSV: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_RX_ALOG_INTF_OBSV)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_READ_EQCODE: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_READ_EQCODE)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_RX_READ_OFFSETCODE: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_RX_READ_OFFSETCODE)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_TX_BIST_STATUS: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_TX_BIST_STATUS)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_TX_BIST_ERROR_COUNT1: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_TX_BIST_ERROR_COUNT1)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_TX_BIST_ERROR_COUNT2: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_TX_BIST_ERROR_COUNT2)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_TX_TX_ALOG_INTF_OBSV: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_TX_TX_ALOG_INTF_OBSV)); - PCIE_DUMP(dev, "PCIe: RC%d QSERDES_TX_PWM_DEC_STATUS: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + QSERDES_TX_PWM_DEC_STATUS)); - PCIE_DUMP(dev, "PCIe: RC%d PCIE_PHY_BIST_CHK_ERR_CNT_L: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_BIST_CHK_ERR_CNT_L)); - PCIE_DUMP(dev, "PCIe: RC%d PCIE_PHY_BIST_CHK_ERR_CNT_H: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_BIST_CHK_ERR_CNT_H)); - PCIE_DUMP(dev, "PCIe: RC%d PCIE_PHY_BIST_CHK_STATUS: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_BIST_CHK_STATUS)); - PCIE_DUMP(dev, "PCIe: RC%d PCIE_PHY_LFPS_RXTERM_IRQ_SOURCE: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_LFPS_RXTERM_IRQ_SOURCE)); - PCIE_DUMP(dev, "PCIe: RC%d PCIE_PHY_PCS_STATUS: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_PCS_STATUS)); - PCIE_DUMP(dev, "PCIe: RC%d PCIE_PHY_PCS_STATUS2: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_PCS_STATUS2)); - PCIE_DUMP(dev, "PCIe: RC%d PCIE_PHY_REVISION_ID0: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_REVISION_ID0)); - PCIE_DUMP(dev, "PCIe: RC%d PCIE_PHY_REVISION_ID1: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_REVISION_ID1)); - PCIE_DUMP(dev, "PCIe: RC%d PCIE_PHY_REVISION_ID2: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_REVISION_ID2)); - PCIE_DUMP(dev, "PCIe: RC%d PCIE_PHY_REVISION_ID3: 0x%x\n", - dev->rc_idx, readl_relaxed(dev->phy + PCIE_PHY_REVISION_ID3)); + msm_pcie_write_reg(dev->phy, QSERDES_COM_DEBUG_BUS_SEL, + write_val); + + PCIE_DUMP(dev, + "PCIe: RC%d to QSERDES_COM_DEBUG_BUS_SEL: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS_SEL)); + PCIE_DUMP(dev, + "PCIe: RC%d QSERDES_COM_DEBUG_BUS0: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS0)); + PCIE_DUMP(dev, + "PCIe: RC%d QSERDES_COM_DEBUG_BUS1: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS1)); + PCIE_DUMP(dev, + "PCIe: RC%d QSERDES_COM_DEBUG_BUS2: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS2)); + PCIE_DUMP(dev, + "PCIe: RC%d QSERDES_COM_DEBUG_BUS3: 0x%x\n\n", + dev->rc_idx, + readl_relaxed(dev->phy + QSERDES_COM_DEBUG_BUS3)); + } + + for (i = 0; i < 3; i++) { + write_val = 0x1 + i; + + msm_pcie_write_reg(dev->phy, + QSERDES_TX_N_DEBUG_BUS_SEL(dev->rc_idx, + dev->common_phy), + write_val); + msm_pcie_write_reg(dev->phy, + PCIE_N_TEST_CONTROL4(dev->rc_idx, dev->common_phy), + 0x30); + msm_pcie_write_reg(dev->phy, + PCIE_N_TEST_CONTROL5(dev->rc_idx, dev->common_phy), + 0x31); + msm_pcie_write_reg(dev->phy, + PCIE_N_TEST_CONTROL6(dev->rc_idx, dev->common_phy), + 0x32); + msm_pcie_write_reg(dev->phy, + PCIE_N_TEST_CONTROL7(dev->rc_idx, dev->common_phy), + 0x33); + + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_N_TEST_CONTROL4: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_N_TEST_CONTROL4(dev->rc_idx, + dev->common_phy))); + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_N_TEST_CONTROL5: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_N_TEST_CONTROL5(dev->rc_idx, + dev->common_phy))); + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_N_TEST_CONTROL6: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_N_TEST_CONTROL6(dev->rc_idx, + dev->common_phy))); + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_N_TEST_CONTROL7: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_N_TEST_CONTROL7(dev->rc_idx, + dev->common_phy))); + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_PHY_DEBUG_BUS_0_STATUS: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_N_DEBUG_BUS_0_STATUS(dev->rc_idx, + dev->common_phy))); + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_N_DEBUG_BUS_1_STATUS: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_N_DEBUG_BUS_1_STATUS(dev->rc_idx, + dev->common_phy))); + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_N_DEBUG_BUS_2_STATUS: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_N_DEBUG_BUS_2_STATUS(dev->rc_idx, + dev->common_phy))); + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_N_DEBUG_BUS_3_STATUS: 0x%x\n\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_N_DEBUG_BUS_3_STATUS(dev->rc_idx, + dev->common_phy))); + } + + if (dev->common_phy) { + msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE0_INDEX, + 0x01); + msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE1_INDEX, + 0x02); + msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE2_INDEX, + 0x03); + msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE3_INDEX, + 0x04); + + PCIE_DUMP(dev, + "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE0_INDEX: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_COM_DEBUG_BUS_BYTE0_INDEX)); + PCIE_DUMP(dev, + "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE1_INDEX: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_COM_DEBUG_BUS_BYTE1_INDEX)); + PCIE_DUMP(dev, + "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE2_INDEX: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_COM_DEBUG_BUS_BYTE2_INDEX)); + PCIE_DUMP(dev, + "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE3_INDEX: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_COM_DEBUG_BUS_BYTE3_INDEX)); + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_COM_DEBUG_BUS_0_STATUS: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_COM_DEBUG_BUS_0_STATUS)); + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_COM_DEBUG_BUS_1_STATUS: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_COM_DEBUG_BUS_1_STATUS)); + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_COM_DEBUG_BUS_2_STATUS: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_COM_DEBUG_BUS_2_STATUS)); + PCIE_DUMP(dev, + "PCIe: RC%d PCIE_COM_DEBUG_BUS_3_STATUS: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_COM_DEBUG_BUS_3_STATUS)); + + msm_pcie_write_reg(dev->phy, PCIE_COM_DEBUG_BUS_BYTE0_INDEX, + 0x05); + + PCIE_DUMP(dev, + "PCIe: RC%d to PCIE_COM_DEBUG_BUS_BYTE0_INDEX: 0x%x\n", + dev->rc_idx, + readl_relaxed(dev->phy + + PCIE_COM_DEBUG_BUS_BYTE0_INDEX)); + PCIE_DUMP(dev, + "PCIe: RC%d QSERDES_COM_DEBUG_BUS0: 0x%x\n\n", + dev->rc_idx, + readl_relaxed(dev->phy + + QSERDES_COM_DEBUG_BUS0)); + } size = resource_size(dev->res[MSM_PCIE_RES_PHY].resource); for (i = 0; i < size; i += 32) { @@ -964,73 +1054,141 @@ static void pcie_phy_dump(struct msm_pcie_dev_t *dev) static void pcie_phy_init(struct msm_pcie_dev_t *dev) { - - PCIE_DBG(dev, "RC%d: Initializing 20nm QMP phy - 19.2MHz\n", + PCIE_DBG(dev, + "RC%d: Initializing 14nm QMP phy - 19.2MHz with Common Mode Clock (SSC ON)\n", dev->rc_idx); - msm_pcie_write_reg(dev->phy, PCIE_PHY_POWER_DOWN_CONTROL, 0x03); + if (dev->common_phy) + msm_pcie_write_reg(dev->phy, PCIE_COM_POWER_DOWN_CONTROL, 0x01); - msm_pcie_write_reg(dev->phy, QSERDES_COM_SYSCLK_EN_SEL_TXBAND, 0x08); - msm_pcie_write_reg(dev->phy, QSERDES_COM_DEC_START1, 0x82); - msm_pcie_write_reg(dev->phy, QSERDES_COM_DEC_START2, 0x03); - msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START1, 0xD5); - msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START2, 0xAA); - msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START3, 0x4D); - msm_pcie_write_reg(dev->phy, QSERDES_COM_PLLLOCK_CMP_EN, 0x03); - msm_pcie_write_reg(dev->phy, QSERDES_COM_PLLLOCK_CMP1, 0x06); - msm_pcie_write_reg(dev->phy, QSERDES_COM_PLLLOCK_CMP2, 0x1A); - msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_CRCTRL, 0x7C); - msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_CP_SETI, 0x1F); - msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_IP_SETP, 0x12); - msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_CP_SETP, 0x0F); - msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_IP_SETI, 0x01); - msm_pcie_write_reg(dev->phy, QSERDES_COM_IE_TRIM, 0x0F); - msm_pcie_write_reg(dev->phy, QSERDES_COM_IP_TRIM, 0x0F); - msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_CNTRL, 0x46); + msm_pcie_write_reg(dev->phy, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1C); + msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_ENABLE1, 0x1F); + msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_SELECT, 0x30); + msm_pcie_write_reg(dev->phy, QSERDES_COM_BG_CTRL, 0x00); + msm_pcie_write_reg(dev->phy, QSERDES_COM_CMN_CONFIG, 0x06); + msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP_EN, 0x00); + msm_pcie_write_reg(dev->phy, QSERDES_COM_RESETSM_CNTRL, 0x01); + msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_MAP, 0x00); + msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE2_MODE0, 0x02); + msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE1_MODE0, 0x24); + msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_TIMER1, 0xFF); + msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_TIMER2, 0x1F); + msm_pcie_write_reg(dev->phy, QSERDES_COM_RESTRIM_CTRL, 0x00); + msm_pcie_write_reg(dev->phy, QSERDES_COM_HSCLK_SEL, 0x01); + msm_pcie_write_reg(dev->phy, QSERDES_COM_SVS_MODE_CLK_SEL, 0x01); + msm_pcie_write_reg(dev->phy, QSERDES_COM_CORE_CLK_EN, 0x6E); + msm_pcie_write_reg(dev->phy, QSERDES_COM_CORECLK_DIV, 0x0A); + msm_pcie_write_reg(dev->phy, QSERDES_COM_BG_TIMER, 0x0A); + msm_pcie_write_reg(dev->phy, QSERDES_COM_DEC_START_MODE0, 0x82); + msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03); + msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55); + msm_pcie_write_reg(dev->phy, QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55); + msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP3_MODE0, 0x00); + msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP2_MODE0, 0x34); + msm_pcie_write_reg(dev->phy, QSERDES_COM_LOCK_CMP1_MODE0, 0x14); + msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_SELECT, 0x31); + msm_pcie_write_reg(dev->phy, QSERDES_COM_SYS_CLK_CTRL, 0x06); + msm_pcie_write_reg(dev->phy, QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1F); + msm_pcie_write_reg(dev->phy, QSERDES_COM_SYSCLK_EN_SEL, 0x04); + msm_pcie_write_reg(dev->phy, QSERDES_COM_CP_CTRL_MODE0, 0x0B); + msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_RCTRL_MODE0, 0x16); + msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_CCTRL_MODE0, 0x28); + msm_pcie_write_reg(dev->phy, QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00); + msm_pcie_write_reg(dev->phy, QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80); + msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_EN_CENTER, 0x01); + msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_PER1, 0x31); + msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_PER2, 0x01); + msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_ADJ_PER1, 0x02); + msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_ADJ_PER2, 0x00); + msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_STEP_SIZE1, 0x2f); + msm_pcie_write_reg(dev->phy, QSERDES_COM_SSC_STEP_SIZE2, 0x19); - /* CDR Settings */ - msm_pcie_write_reg(dev->phy, QSERDES_RX_CDR_CONTROL1, 0xF4); - msm_pcie_write_reg(dev->phy, QSERDES_RX_CDR_CONTROL_HALF, 0x2C); + msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE_CTRL, 0x1C); + msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE1_MODE0, 0x3F); + msm_pcie_write_reg(dev->phy, QSERDES_COM_VCO_TUNE2_MODE0, 0x01); + msm_pcie_write_reg(dev->phy, QSERDES_COM_RESCODE_DIV_NUM, 0x15); + msm_pcie_write_reg(dev->phy, QSERDES_COM_BG_TRIM, 0x0F); + msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_IVCO, 0x0F); - msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_VCOTAIL_EN, 0xE1); + msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_EP_DIV, 0x19); + msm_pcie_write_reg(dev->phy, QSERDES_COM_CLK_ENABLE1, 0x1F); - /* Calibration Settings */ - msm_pcie_write_reg(dev->phy, QSERDES_COM_RESETSM_CNTRL, 0x91); - msm_pcie_write_reg(dev->phy, QSERDES_COM_RESETSM_CNTRL2, 0x07); + if (dev->common_phy) { + msm_pcie_write_reg(dev->phy, PCIE_COM_SW_RESET, 0x00); + msm_pcie_write_reg(dev->phy, PCIE_COM_START_CONTROL, 0x03); + } +} - /* Additional writes */ - msm_pcie_write_reg(dev->phy, QSERDES_COM_RES_CODE_START_SEG1, 0x20); - msm_pcie_write_reg(dev->phy, QSERDES_COM_RES_CODE_CAL_CSR, 0x77); - msm_pcie_write_reg(dev->phy, QSERDES_COM_RES_TRIM_CONTROL, 0x15); - msm_pcie_write_reg(dev->phy, QSERDES_TX_RCV_DETECT_LVL, 0x03); - msm_pcie_write_reg(dev->phy, QSERDES_RX_UCDR_FO_GAIN, 0x09); - msm_pcie_write_reg(dev->phy, QSERDES_RX_UCDR_SO_GAIN, 0x04); - msm_pcie_write_reg(dev->phy, QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, - 0x49); - msm_pcie_write_reg(dev->phy, QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF); - msm_pcie_write_reg(dev->phy, QSERDES_RX_RX_EQ_GAIN1_MSB, 0x1F); - msm_pcie_write_reg(dev->phy, QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF); - msm_pcie_write_reg(dev->phy, QSERDES_RX_RX_EQ_GAIN2_MSB, 0x00); - msm_pcie_write_reg(dev->phy, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1E); - msm_pcie_write_reg(dev->phy, QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, - 0x67); - msm_pcie_write_reg(dev->phy, QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80); - msm_pcie_write_reg(dev->phy, QSERDES_RX_SIGDET_ENABLES, 0x40); - msm_pcie_write_reg(dev->phy, QSERDES_RX_SIGDET_CNTRL, 0xB0); - msm_pcie_write_reg(dev->phy, QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x06); - msm_pcie_write_reg(dev->phy, QSERDES_COM_PLL_RXTXEPCLK_EN, 0x10); - msm_pcie_write_reg(dev->phy, PCIE_PHY_ENDPOINT_REFCLK_DRIVE, 0x10); - msm_pcie_write_reg(dev->phy, PCIE_PHY_POWER_STATE_CONFIG1, 0xA3); - msm_pcie_write_reg(dev->phy, PCIE_PHY_POWER_STATE_CONFIG2, 0x4B); - msm_pcie_write_reg(dev->phy, PCIE_PHY_RX_IDLE_DTCT_CNTRL, 0x4D); +static void pcie_pcs_port_phy_init(struct msm_pcie_dev_t *dev) +{ + u8 common_phy; - msm_pcie_write_reg(dev->phy, PCIE_PHY_SW_RESET, 0x00); - msm_pcie_write_reg(dev->phy, PCIE_PHY_START, 0x03); + PCIE_DBG(dev, "RC%d: Initializing PCIe PHY Port\n", dev->rc_idx); + + if (dev->common_phy) + common_phy = 1; + else + common_phy = 0; + + msm_pcie_write_reg(dev->phy, + QSERDES_TX_N_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN(dev->rc_idx, + common_phy), 0x45); + msm_pcie_write_reg(dev->phy, + QSERDES_TX_N_LANE_MODE(dev->rc_idx, common_phy), + 0x02); + + msm_pcie_write_reg(dev->phy, + QSERDES_RX_N_SIGDET_ENABLES(dev->rc_idx, common_phy), + 0x10); + msm_pcie_write_reg(dev->phy, + QSERDES_RX_N_SIGDET_LVL(dev->rc_idx, common_phy), + 0x1B); + msm_pcie_write_reg(dev->phy, + QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL2(dev->rc_idx, common_phy), + 0x71); + msm_pcie_write_reg(dev->phy, + QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL3(dev->rc_idx, common_phy), + 0x5E); + msm_pcie_write_reg(dev->phy, + QSERDES_RX_N_RX_EQU_ADAPTOR_CNTRL4(dev->rc_idx, common_phy), + 0xBB); + msm_pcie_write_reg(dev->phy, + QSERDES_RX_N_UCDR_SO_GAIN(dev->rc_idx, common_phy), + 0x04); + msm_pcie_write_reg(dev->phy, + QSERDES_RX_N_UCDR_SO_SATURATION_AND_ENABLE(dev->rc_idx, + common_phy), 0x4B); + msm_pcie_write_reg(dev->phy, + QSERDES_RX_N_SIGDET_DEGLITCH_CNTRL(dev->rc_idx, common_phy), + 0x08); + + msm_pcie_write_reg(dev->phy, + PCIE_N_ENDPOINT_REFCLK_DRIVE(dev->rc_idx, common_phy), + 0x04); + msm_pcie_write_reg(dev->phy, + PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, common_phy), + 0x02); + msm_pcie_write_reg(dev->phy, + PCIE_N_POWER_STATE_CONFIG4(dev->rc_idx, common_phy), + 0x02); + msm_pcie_write_reg(dev->phy, + PCIE_N_POWER_STATE_CONFIG1(dev->rc_idx, common_phy), + 0x63); + + msm_pcie_write_reg(dev->phy, + PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, common_phy), + 0x03); + msm_pcie_write_reg(dev->phy, + PCIE_N_SW_RESET(dev->rc_idx, common_phy), + 0x00); + msm_pcie_write_reg(dev->phy, + PCIE_N_START_CONTROL(dev->rc_idx, common_phy), + 0x0A); } static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev) { - if (readl_relaxed(dev->phy + PCIE_PHY_PCS_STATUS) & BIT(6)) + if (!(readl_relaxed(dev->phy + PCIE_COM_PCS_READY_STATUS) & 0x1)) return false; else return true; @@ -1261,6 +1419,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) dev->bus_client); pr_alert("n_fts: %d\n", dev->n_fts); + pr_alert("common_phy: %d\n", + dev->common_phy); pr_alert("ep_latency: %dms\n", dev->ep_latency); pr_alert("current_bdf: 0x%x\n", @@ -1365,7 +1525,7 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev, break; case 1: /* disable link */ pr_alert("\n\nPCIe: RC%d: disable link\n\n", dev->rc_idx); - ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, 1, + ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, 0, dev->dev, NULL, MSM_PCIE_CONFIG_NO_CFG_RESTORE); if (ret) @@ -1378,7 +1538,7 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev, case 2: /* enable link and recover config space for RC and EP */ pr_alert("\n\nPCIe: RC%d: enable link and recover config space\n\n", dev->rc_idx); - ret = msm_pcie_pm_control(MSM_PCIE_RESUME, 1, + ret = msm_pcie_pm_control(MSM_PCIE_RESUME, 0, dev->dev, NULL, MSM_PCIE_CONFIG_NO_CFG_RESTORE); if (ret) @@ -1395,7 +1555,7 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev, */ pr_alert("\n\nPCIe: RC%d: disable and enable link then recover config space\n\n", dev->rc_idx); - ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, 1, + ret = msm_pcie_pm_control(MSM_PCIE_SUSPEND, 0, dev->dev, NULL, MSM_PCIE_CONFIG_NO_CFG_RESTORE); if (ret) @@ -1403,7 +1563,7 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev, __func__); else pr_alert("PCIe:%s:disabled link\n", __func__); - ret = msm_pcie_pm_control(MSM_PCIE_RESUME, 1, + ret = msm_pcie_pm_control(MSM_PCIE_RESUME, 0, dev->dev, NULL, MSM_PCIE_CONFIG_NO_CFG_RESTORE); if (ret) @@ -2271,8 +2431,7 @@ static inline int msm_pcie_oper_conf(struct pci_bus *bus, u32 devfn, int oper, u32 bdf = BDF_OFFSET(bus->number, devfn); int i; - dev = ((struct msm_pcie_dev_t *) - (((struct pci_sys_data *)bus->sysdata)->private_data)); + dev = bus->sysdata; if (!dev) { pr_err("PCIe: No device found for this bus.\n"); @@ -2543,6 +2702,17 @@ static int msm_pcie_clk_init(struct msm_pcie_dev_t *dev) return rc; } + if (dev->gdsc_smmu) { + rc = regulator_enable(dev->gdsc_smmu); + + if (rc) { + PCIE_ERR(dev, + "PCIe: fail to enable SMMU GDSC for RC%d (%s)\n", + dev->rc_idx, dev->pdev->name); + return rc; + } + } + if (dev->bus_client) { rc = msm_bus_scale_client_update_request(dev->bus_client, 1); if (rc) { @@ -2563,7 +2733,7 @@ static int msm_pcie_clk_init(struct msm_pcie_dev_t *dev) if (!info->hdl) continue; - if (i == MSM_PCIE_MAX_CLK-1) + if (i >= MSM_PCIE_MAX_CLK - (dev->common_phy ? 4 : 1)) clk_reset(info->hdl, CLK_RESET_DEASSERT); if (info->freq) { @@ -2599,6 +2769,9 @@ static int msm_pcie_clk_init(struct msm_pcie_dev_t *dev) clk_disable_unprepare(hdl); } + if (dev->gdsc_smmu) + regulator_disable(dev->gdsc_smmu); + regulator_disable(dev->gdsc); } @@ -2628,6 +2801,9 @@ static void msm_pcie_clk_deinit(struct msm_pcie_dev_t *dev) dev->rc_idx); } + if (dev->gdsc_smmu) + regulator_disable(dev->gdsc_smmu); + regulator_disable(dev->gdsc); } @@ -3055,6 +3231,14 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev, goto out; } + dev->gdsc_smmu = devm_regulator_get(&pdev->dev, "gdsc-smmu"); + + if (IS_ERR(dev->gdsc_smmu)) { + PCIE_DBG(dev, "PCIe: RC%d SMMU GDSC does not exist", + dev->rc_idx); + dev->gdsc_smmu = NULL; + } + dev->gpio_n = 0; for (i = 0; i < MSM_PCIE_MAX_GPIO; i++) { gpio_info = &dev->gpio[i]; @@ -3275,9 +3459,18 @@ int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) writel_relaxed(0x365E, dev->parf + PCIE20_PARF_SYS_CTRL); - if (dev->dev_mem_res->end - dev->dev_mem_res->start > SZ_8M) + msm_pcie_write_mask(dev->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL, + 0, BIT(4)); + + if (dev->dev_mem_res->end - dev->dev_mem_res->start > SZ_16M) + writel_relaxed(SZ_32M, dev->parf + + PCIE20_PARF_SLV_ADDR_SPACE_SIZE); + else if (dev->dev_mem_res->end - dev->dev_mem_res->start > SZ_8M) writel_relaxed(SZ_16M, dev->parf + PCIE20_PARF_SLV_ADDR_SPACE_SIZE); + else + writel_relaxed(SZ_8M, dev->parf + + PCIE20_PARF_SLV_ADDR_SPACE_SIZE); if (dev->use_msi) { PCIE_DBG(dev, "RC%d: enable WR halt.\n", dev->rc_idx); @@ -3286,7 +3479,8 @@ int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) } /* init PCIe PHY */ - pcie_phy_init(dev); + if (!num_rc_on) + pcie_phy_init(dev); if (options & PM_PIPE_CLK) { usleep_range(PHY_STABILIZATION_DELAY_US_MIN, @@ -3321,6 +3515,8 @@ int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) goto link_fail; } + pcie_pcs_port_phy_init(dev); + if (dev->ep_latency) usleep_range(dev->ep_latency * 1000, dev->ep_latency * 1000); @@ -3377,11 +3573,21 @@ int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options) dev->power_on = true; dev->suspending = false; dev->link_turned_on_counter++; + num_rc_on++; + goto out; link_fail: - msm_pcie_write_reg(dev->phy, PCIE_PHY_SW_RESET, 0x1); - msm_pcie_write_reg(dev->phy, PCIE_PHY_POWER_DOWN_CONTROL, 0); + msm_pcie_write_reg(dev->phy, + PCIE_N_SW_RESET(dev->rc_idx, dev->common_phy), 0x1); + msm_pcie_write_reg(dev->phy, + PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, dev->common_phy), 0); + if (!num_rc_on) { + PCIE_DBG(dev, "PCIe: RC%d is powering down the common phy\n", + dev->rc_idx); + msm_pcie_write_reg(dev->phy, PCIE_COM_SW_RESET, 0x1); + msm_pcie_write_reg(dev->phy, PCIE_COM_POWER_DOWN_CONTROL, 0); + } msm_pcie_pipe_clk_deinit(dev); msm_pcie_clk_deinit(dev); clk_fail: @@ -3409,6 +3615,7 @@ void msm_pcie_disable(struct msm_pcie_dev_t *dev, u32 options) dev->link_status = MSM_PCIE_LINK_DISABLED; dev->power_on = false; dev->link_turned_off_counter++; + num_rc_on--; PCIE_INFO(dev, "PCIe: Assert the reset of endpoint of RC%d.\n", dev->rc_idx); @@ -3416,8 +3623,17 @@ void msm_pcie_disable(struct msm_pcie_dev_t *dev, u32 options) gpio_set_value(dev->gpio[MSM_PCIE_GPIO_PERST].num, dev->gpio[MSM_PCIE_GPIO_PERST].on); - msm_pcie_write_reg(dev->phy, PCIE_PHY_SW_RESET, 0x1); - msm_pcie_write_reg(dev->phy, PCIE_PHY_POWER_DOWN_CONTROL, 0); + msm_pcie_write_reg(dev->phy, + PCIE_N_SW_RESET(dev->rc_idx, dev->common_phy), 0x1); + msm_pcie_write_reg(dev->phy, + PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, dev->common_phy), 0); + + if (!num_rc_on) { + PCIE_DBG(dev, "PCIe: RC%d is powering down the common phy\n", + dev->rc_idx); + msm_pcie_write_reg(dev->phy, PCIE_COM_SW_RESET, 0x1); + msm_pcie_write_reg(dev->phy, PCIE_COM_POWER_DOWN_CONTROL, 0); + } if (options & PM_CLK) { msm_pcie_write_mask(dev->parf + PCIE20_PARF_PHY_CTRL, 0, @@ -3434,88 +3650,6 @@ void msm_pcie_disable(struct msm_pcie_dev_t *dev, u32 options) mutex_unlock(&dev->setup_lock); } -static int msm_pcie_setup(int nr, struct pci_sys_data *sys) -{ - struct msm_pcie_dev_t *dev = - (struct msm_pcie_dev_t *)(sys->private_data); - - PCIE_DBG(dev, "bus %d\n", nr); - /* - * specify linux PCI framework to allocate device memory (BARs) - * from msm_pcie_dev.dev_mem_res resource. - */ - sys->mem_offset = 0; - sys->io_offset = 0; - - pci_add_resource(&sys->resources, dev->dev_io_res); - pci_add_resource(&sys->resources, dev->dev_mem_res); - return 1; -} - -static struct pci_bus *msm_pcie_scan_bus(int nr, - struct pci_sys_data *sys) -{ - struct pci_bus *bus = NULL; - struct msm_pcie_dev_t *dev = - (struct msm_pcie_dev_t *)(sys->private_data); - - PCIE_DBG(dev, "bus %d\n", nr); - - bus = pci_scan_root_bus(NULL, sys->busnr, &msm_pcie_ops, sys, - &sys->resources); - - return bus; -} - -static int msm_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - struct msm_pcie_dev_t *pcie_dev = PCIE_BUS_PRIV_DATA(dev); - int ret = 0; - - PCIE_DBG(pcie_dev, "rc %s slot %d pin %d\n", pcie_dev->pdev->name, - slot, pin); - - switch (pin) { - case 1: - ret = pcie_dev->irq[MSM_PCIE_INT_A].num; - break; - case 2: - ret = pcie_dev->irq[MSM_PCIE_INT_B].num; - break; - case 3: - ret = pcie_dev->irq[MSM_PCIE_INT_C].num; - break; - case 4: - ret = pcie_dev->irq[MSM_PCIE_INT_D].num; - break; - default: - PCIE_ERR(pcie_dev, "PCIe: RC%d: unsupported pin number.\n", - pcie_dev->rc_idx); - } - - return ret; -} - - -static struct hw_pci msm_pci[MAX_RC_NUM] = { - { - .domain = 0, - .nr_controllers = 1, - .swizzle = pci_common_swizzle, - .setup = msm_pcie_setup, - .scan = msm_pcie_scan_bus, - .map_irq = msm_pcie_map_irq, - }, - { - .domain = 1, - .nr_controllers = 1, - .swizzle = pci_common_swizzle, - .setup = msm_pcie_setup, - .scan = msm_pcie_scan_bus, - .map_irq = msm_pcie_map_irq, - }, -}; - static void msm_pcie_config_ep_aer(struct msm_pcie_dev_t *dev, struct msm_pcie_device_info *ep_dev_info) { @@ -3685,6 +3819,8 @@ int msm_pcie_enumerate(u32 rc_idx) /* kick start ARM PCI configuration framework */ if (!ret) { struct pci_dev *pcidev = NULL; + struct pci_host_bridge *bridge; + resource_size_t lastbus; bool found = false; u32 ids = readl_relaxed(msm_pcie_dev[rc_idx].dm_core); u32 vendor_id = ids & 0xffff; @@ -3693,9 +3829,20 @@ int msm_pcie_enumerate(u32 rc_idx) PCIE_DBG(dev, "vendor-id:0x%x device_id:0x%x\n", vendor_id, device_id); - msm_pci[rc_idx].private_data = (void **)&dev; - pci_common_init(&msm_pci[rc_idx]); - /* This has to happen only once */ + bridge = of_create_pci_host_bridge(&dev->pdev->dev, + &msm_pcie_ops, + dev); + + if (IS_ERR_OR_NULL(bridge)) + return PTR_ERR(bridge); + + pci_add_flags(PCI_ENABLE_PROC_DOMAINS); + pci_add_flags(PCI_REASSIGN_ALL_BUS | + PCI_REASSIGN_ALL_RSRC); + + lastbus = pci_rescan_bus(bridge->bus); + pci_bus_update_busn_res_end(bridge->bus, lastbus); + dev->enumerated = true; msm_pcie_write_mask(dev->dm_core + @@ -4581,6 +4728,13 @@ static int msm_pcie_probe(struct platform_device *pdev) PCIE_DBG(&msm_pcie_dev[rc_idx], "n-fts: 0x%x.\n", msm_pcie_dev[rc_idx].n_fts); + msm_pcie_dev[rc_idx].common_phy = + of_property_read_bool((&pdev->dev)->of_node, + "qcom,common-phy"); + PCIE_DBG(&msm_pcie_dev[rc_idx], + "PCIe: RC%d: Common PHY does %s exist.\n", + rc_idx, msm_pcie_dev[rc_idx].common_phy ? "" : "not"); + msm_pcie_dev[rc_idx].ext_ref_clk = of_property_read_bool((&pdev->dev)->of_node, "qcom,ext-ref-clk"); @@ -5156,6 +5310,8 @@ int msm_pcie_pm_control(enum msm_pcie_pm_opt pm_opt, u32 busnr, void *user, } for (i = 0; i < MAX_DEVICE_NUM; i++) { + if (!busnr) + break; if (user == pcie_dev->pcidev_table[i].dev) { if (busnr == pcie_dev->pcidev_table[i].bdf >> 24) { break;