evie/android_kernel_oneplus_msm8998
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Merge "msm: camera: isp: Check reg update miss only for PIX stream"

Browse source
This commit is contained in:
Linux Build Service Account 2016-12-06 14:33:04 -08:00 • committed by Gerrit - the friendly Code Review server
commit fec46a2e93
10 changed files with 226 additions and 432 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
drivers/media/platform/msm/camera_v2/isp/msm_isp.h
View file

@ -192,15 +192,12 @@ struct msm_vfe_axi_ops {
uint8_t plane_idx);
void (*clear_wm_xbar_reg)(struct vfe_device *vfe_dev,
struct msm_vfe_axi_stream *stream_info, uint8_t plane_idx);
void (*cfg_ub)(struct vfe_device *vfe_dev);
void (*cfg_ub)(struct vfe_device *vfe_dev,
enum msm_vfe_input_src frame_src);
void (*read_wm_ping_pong_addr)(struct vfe_device *vfe_dev);
void (*update_ping_pong_addr)(void __iomem *vfe_base,
uint8_t wm_idx, uint32_t pingpong_bit, dma_addr_t paddr,
int32_t buf_size);
uint32_t (*get_wm_mask)(uint32_t irq_status0, uint32_t irq_status1);
uint32_t (*get_comp_mask)(uint32_t irq_status0, uint32_t irq_status1);
uint32_t (*get_pingpong_status)(struct vfe_device *vfe_dev);
@ -209,6 +206,8 @@ struct msm_vfe_axi_ops {
uint32_t enable_camif);
void (*update_cgc_override)(struct vfe_device *vfe_dev,
uint8_t wm_idx, uint8_t cgc_override);
uint32_t (*ub_reg_offset)(struct vfe_device *vfe_dev, int idx);
uint32_t (*get_ub_size)(struct vfe_device *vfe_dev);
};
struct msm_vfe_core_ops {

84
drivers/media/platform/msm/camera_v2/isp/msm_isp32.c
View file

@ -60,6 +60,16 @@ static struct msm_cam_clk_info msm_vfe32_2_clk_info[] = {
{"csi_vfe_clk", -1},
};
static uint32_t msm_vfe32_ub_reg_offset(struct vfe_device *vfe_dev, int idx)
{
return (VFE32_WM_BASE(idx) + 0x10);
}
static uint32_t msm_vfe32_get_ub_size(struct vfe_device *vfe_dev)
{
return MSM_ISP32_TOTAL_WM_UB;
}
static int32_t msm_vfe32_init_qos_parms(struct vfe_device *vfe_dev,
struct msm_vfe_hw_init_parms *qos_parms,
struct msm_vfe_hw_init_parms *ds_parms)
@ -1099,76 +1109,6 @@ static void msm_vfe32_axi_clear_wm_xbar_reg(
msm_camera_io_w(xbar_reg_cfg, vfe_dev->vfe_base + VFE32_XBAR_BASE(wm));
}
static void msm_vfe32_cfg_axi_ub_equal_default(struct vfe_device *vfe_dev)
{
int i;
uint32_t ub_offset = 0;
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
uint32_t total_image_size = 0;
uint32_t num_used_wms = 0;
uint32_t prop_size = 0;
uint32_t wm_ub_size;
uint64_t delta;
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
if (axi_data->free_wm[i] > 0) {
num_used_wms++;
total_image_size += axi_data->wm_image_size[i];
}
}
prop_size = MSM_ISP32_TOTAL_WM_UB -
axi_data->hw_info->min_wm_ub * num_used_wms;
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
if (axi_data->free_wm[i]) {
delta =
(uint64_t)(axi_data->wm_image_size[i] *
prop_size);
do_div(delta, total_image_size);
wm_ub_size = axi_data->hw_info->min_wm_ub +
(uint32_t)delta;
msm_camera_io_w(ub_offset << 16 |
(wm_ub_size - 1), vfe_dev->vfe_base +
VFE32_WM_BASE(i) + 0xC);
ub_offset += wm_ub_size;
} else {
msm_camera_io_w(0,
vfe_dev->vfe_base + VFE32_WM_BASE(i) + 0xC);
}
}
}
static void msm_vfe32_cfg_axi_ub_equal_slicing(struct vfe_device *vfe_dev)
{
int i;
uint32_t ub_offset = 0;
uint32_t final_ub_slice_size;
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
if (ub_offset + VFE32_EQUAL_SLICE_UB > VFE32_AXI_SLICE_UB) {
final_ub_slice_size = VFE32_AXI_SLICE_UB - ub_offset;
msm_camera_io_w(ub_offset << 16 |
(final_ub_slice_size - 1), vfe_dev->vfe_base +
VFE32_WM_BASE(i) + 0xC);
ub_offset += final_ub_slice_size;
} else {
msm_camera_io_w(ub_offset << 16 |
(VFE32_EQUAL_SLICE_UB - 1), vfe_dev->vfe_base +
VFE32_WM_BASE(i) + 0xC);
ub_offset += VFE32_EQUAL_SLICE_UB;
}
}
}
static void msm_vfe32_cfg_axi_ub(struct vfe_device *vfe_dev)
{
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
axi_data->wm_ub_cfg_policy = MSM_WM_UB_CFG_DEFAULT;
if (axi_data->wm_ub_cfg_policy == MSM_WM_UB_EQUAL_SLICING)
msm_vfe32_cfg_axi_ub_equal_slicing(vfe_dev);
else
msm_vfe32_cfg_axi_ub_equal_default(vfe_dev);
}
static void msm_vfe32_update_ping_pong_addr(void __iomem *vfe_base,
uint8_t wm_idx, uint32_t pingpong_bit, dma_addr_t paddr,
int32_t buf_size)
@ -1506,13 +1446,15 @@ struct msm_vfe_hardware_info vfe32_hw_info = {
.clear_wm_reg = msm_vfe32_axi_clear_wm_reg,
.cfg_wm_xbar_reg = msm_vfe32_axi_cfg_wm_xbar_reg,
.clear_wm_xbar_reg = msm_vfe32_axi_clear_wm_xbar_reg,
.cfg_ub = msm_vfe32_cfg_axi_ub,
.cfg_ub = msm_vfe47_cfg_axi_ub,
.update_ping_pong_addr =
msm_vfe32_update_ping_pong_addr,
.get_comp_mask = msm_vfe32_get_comp_mask,
.get_wm_mask = msm_vfe32_get_wm_mask,
.get_pingpong_status = msm_vfe32_get_pingpong_status,
.halt = msm_vfe32_axi_halt,
.ub_reg_offset = msm_vfe40_ub_reg_offset,
.get_ub_size = msm_vfe40_get_ub_size,
},
.core_ops = {
.reg_update = msm_vfe32_reg_update,

118
drivers/media/platform/msm/camera_v2/isp/msm_isp40.c
View file

@ -97,6 +97,20 @@ static uint8_t stats_pingpong_offset_map[] = {
#define VFE40_CLK_IDX 2
static uint32_t msm_vfe40_ub_reg_offset(struct vfe_device *vfe_dev, int idx)
{
return (VFE40_WM_BASE(idx) + 0x10);
}
static uint32_t msm_vfe40_get_ub_size(struct vfe_device *vfe_dev)
{
if (vfe_dev->vfe_hw_version == VFE40_8916_VERSION) {
vfe_dev->ub_info->wm_ub = VFE40_TOTAL_WM_UB_8916;
return VFE40_TOTAL_WM_UB_8916;
}
return VFE40_TOTAL_WM_UB;
}
static void msm_vfe40_config_irq(struct vfe_device *vfe_dev,
uint32_t irq0_mask, uint32_t irq1_mask,
enum msm_isp_irq_operation oper)
@ -740,7 +754,7 @@ static long msm_vfe40_reset_hardware(struct vfe_device *vfe_dev,
msm_camera_io_w(0xFEFFFEFF, vfe_dev->vfe_base + 0x34);
msm_camera_io_w(0x1, vfe_dev->vfe_base + 0x24);
vfe_dev->hw_info->vfe_ops.axi_ops.
reload_wm(vfe_dev, vfe_dev->vfe_base, 0x0001FFFF);
reload_wm(vfe_dev, vfe_dev->vfe_base, 0x0003FFFF);
}
@ -1693,104 +1707,6 @@ static void msm_vfe40_axi_clear_wm_xbar_reg(
vfe_dev->vfe_base + VFE40_XBAR_BASE(wm));
}
static void msm_vfe40_cfg_axi_ub_equal_default(
struct vfe_device *vfe_dev)
{
int i;
uint32_t ub_offset = 0;
struct msm_vfe_axi_shared_data *axi_data =
&vfe_dev->axi_data;
uint32_t total_image_size = 0;
uint8_t num_used_wms = 0;
uint32_t prop_size = 0;
uint32_t wm_ub_size;
uint32_t total_wm_ub;
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
if (axi_data->free_wm[i] > 0) {
num_used_wms++;
total_image_size += axi_data->wm_image_size[i];
}
}
if (vfe_dev->vfe_hw_version == VFE40_8916_VERSION) {
vfe_dev->ub_info->wm_ub = VFE40_TOTAL_WM_UB_8916;
total_wm_ub = VFE40_TOTAL_WM_UB_8916;
} else {
vfe_dev->ub_info->wm_ub = VFE40_TOTAL_WM_UB;
total_wm_ub = VFE40_TOTAL_WM_UB;
}
vfe_dev->ub_info->num_wm = axi_data->hw_info->num_wm;
prop_size = total_wm_ub -
axi_data->hw_info->min_wm_ub * num_used_wms;
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
if (axi_data->free_wm[i]) {
uint64_t delta = 0;
uint64_t temp = (uint64_t)axi_data->wm_image_size[i] *
(uint64_t)prop_size;
do_div(temp, total_image_size);
delta = temp;
wm_ub_size = axi_data->hw_info->min_wm_ub + delta;
msm_camera_io_w(ub_offset << 16 | (wm_ub_size - 1),
vfe_dev->vfe_base + VFE40_WM_BASE(i) + 0x10);
vfe_dev->ub_info->data[i] =
ub_offset << 16 | (wm_ub_size - 1);
vfe_dev->ub_info->addr[i] = VFE40_WM_BASE(i) + 0x10;
ub_offset += wm_ub_size;
} else {
msm_camera_io_w(0,
vfe_dev->vfe_base + VFE40_WM_BASE(i) + 0x10);
vfe_dev->ub_info->data[i] = 0;
vfe_dev->ub_info->addr[i] = VFE40_WM_BASE(i) + 0x10;
}
}
}
static void msm_vfe40_cfg_axi_ub_equal_slicing(
struct vfe_device *vfe_dev)
{
int i;
uint32_t ub_offset = 0;
uint32_t equal_slice_ub;
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
if (vfe_dev->vfe_hw_version == VFE40_8916_VERSION ||
vfe_dev->vfe_hw_version == VFE40_8952_VERSION) {
vfe_dev->ub_info->wm_ub = VFE40_EQUAL_SLICE_UB_8916;
equal_slice_ub = VFE40_EQUAL_SLICE_UB_8916;
} else {
vfe_dev->ub_info->wm_ub = VFE40_EQUAL_SLICE_UB;
equal_slice_ub = VFE40_EQUAL_SLICE_UB;
}
vfe_dev->ub_info->num_wm = axi_data->hw_info->num_wm;
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
msm_camera_io_w(ub_offset << 16 | (equal_slice_ub - 1),
vfe_dev->vfe_base + VFE40_WM_BASE(i) + 0x10);
vfe_dev->ub_info->data[i] =
ub_offset << 16 | (equal_slice_ub - 1);
vfe_dev->ub_info->addr[i] = VFE40_WM_BASE(i) + 0x10;
ub_offset += equal_slice_ub;
}
}
static void msm_vfe40_cfg_axi_ub(struct vfe_device *vfe_dev)
{
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
axi_data->wm_ub_cfg_policy =
(enum msm_wm_ub_cfg_type)vfe_dev->vfe_ub_policy;
ISP_DBG("%s: ub_policy %d\n", __func__, axi_data->wm_ub_cfg_policy);
if (axi_data->wm_ub_cfg_policy == MSM_WM_UB_EQUAL_SLICING) {
vfe_dev->ub_info->policy = MSM_WM_UB_EQUAL_SLICING;
msm_vfe40_cfg_axi_ub_equal_slicing(vfe_dev);
} else {
vfe_dev->ub_info->policy = MSM_WM_UB_CFG_DEFAULT;
msm_vfe40_cfg_axi_ub_equal_default(vfe_dev);
}
}
static void msm_vfe40_read_wm_ping_pong_addr(
struct vfe_device *vfe_dev)
{
@ -2307,7 +2223,7 @@ struct msm_vfe_hardware_info vfe40_hw_info = {
.clear_wm_reg = msm_vfe40_axi_clear_wm_reg,
.cfg_wm_xbar_reg = msm_vfe40_axi_cfg_wm_xbar_reg,
.clear_wm_xbar_reg = msm_vfe40_axi_clear_wm_xbar_reg,
.cfg_ub = msm_vfe40_cfg_axi_ub,
.cfg_ub = msm_vfe47_cfg_axi_ub,
.read_wm_ping_pong_addr =
msm_vfe40_read_wm_ping_pong_addr,
.update_ping_pong_addr =
@ -2319,6 +2235,8 @@ struct msm_vfe_hardware_info vfe40_hw_info = {
.restart = msm_vfe40_axi_restart,
.update_cgc_override =
msm_vfe40_axi_update_cgc_override,
.ub_reg_offset = msm_vfe40_ub_reg_offset,
.get_ub_size = msm_vfe40_get_ub_size,
},
.core_ops = {
.reg_update = msm_vfe40_reg_update,

78
drivers/media/platform/msm/camera_v2/isp/msm_isp44.c
View file

@ -66,6 +66,16 @@ static uint8_t stats_pingpong_offset_map[] = {
#define VFE44_CLK_IDX 2
static uint32_t msm_vfe44_ub_reg_offset(struct vfe_device *vfe_dev, int wm_idx)
{
return (VFE44_WM_BASE(wm_idx) + 0x10);
}
static uint32_t msm_vfe44_get_ub_size(struct vfe_device *vfe_dev)
{
return MSM_ISP44_TOTAL_IMAGE_UB;
}
static void msm_vfe44_config_irq(struct vfe_device *vfe_dev,
uint32_t irq0_mask, uint32_t irq1_mask,
enum msm_isp_irq_operation oper)
@ -577,7 +587,7 @@ static long msm_vfe44_reset_hardware(struct vfe_device *vfe_dev,
msm_camera_io_w(0xFEFFFEFF, vfe_dev->vfe_base + 0x34);
msm_camera_io_w(0x1, vfe_dev->vfe_base + 0x24);
vfe_dev->hw_info->vfe_ops.axi_ops.
reload_wm(vfe_dev, vfe_dev->vfe_base, 0x0001FFFF);
reload_wm(vfe_dev, vfe_dev->vfe_base, 0x0031FFFF);
}
if (blocking_call) {
@ -1262,68 +1272,6 @@ static void msm_vfe44_axi_clear_wm_xbar_reg(
vfe_dev->vfe_base + VFE44_XBAR_BASE(wm));
}
static void msm_vfe44_cfg_axi_ub_equal_default(
struct vfe_device *vfe_dev)
{
int i;
uint32_t ub_offset = 0;
struct msm_vfe_axi_shared_data *axi_data =
&vfe_dev->axi_data;
uint32_t total_image_size = 0;
uint8_t num_used_wms = 0;
uint32_t prop_size = 0;
uint32_t wm_ub_size;
uint64_t delta;
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
if (axi_data->free_wm[i] > 0) {
num_used_wms++;
total_image_size += axi_data->wm_image_size[i];
}
}
prop_size = MSM_ISP44_TOTAL_IMAGE_UB -
axi_data->hw_info->min_wm_ub * num_used_wms;
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
if (axi_data->free_wm[i]) {
delta = (uint64_t)axi_data->wm_image_size[i] *
(uint64_t)prop_size;
do_div(delta, total_image_size);
wm_ub_size = axi_data->hw_info->min_wm_ub +
(uint32_t)delta;
msm_camera_io_w(ub_offset << 16 | (wm_ub_size - 1),
vfe_dev->vfe_base + VFE44_WM_BASE(i) + 0x10);
ub_offset += wm_ub_size;
} else
msm_camera_io_w(0,
vfe_dev->vfe_base + VFE44_WM_BASE(i) + 0x10);
}
}
static void msm_vfe44_cfg_axi_ub_equal_slicing(
struct vfe_device *vfe_dev)
{
int i;
uint32_t ub_offset = 0;
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
uint32_t ub_equal_slice = MSM_ISP44_TOTAL_IMAGE_UB /
axi_data->hw_info->num_wm;
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
msm_camera_io_w(ub_offset << 16 | (ub_equal_slice - 1),
vfe_dev->vfe_base + VFE44_WM_BASE(i) + 0x10);
ub_offset += ub_equal_slice;
}
}
static void msm_vfe44_cfg_axi_ub(struct vfe_device *vfe_dev)
{
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
axi_data->wm_ub_cfg_policy = MSM_WM_UB_CFG_DEFAULT;
if (axi_data->wm_ub_cfg_policy == MSM_WM_UB_EQUAL_SLICING)
msm_vfe44_cfg_axi_ub_equal_slicing(vfe_dev);
else
msm_vfe44_cfg_axi_ub_equal_default(vfe_dev);
}
static void msm_vfe44_read_wm_ping_pong_addr(
struct vfe_device *vfe_dev)
{
@ -1883,7 +1831,7 @@ struct msm_vfe_hardware_info vfe44_hw_info = {
.clear_wm_reg = msm_vfe44_axi_clear_wm_reg,
.cfg_wm_xbar_reg = msm_vfe44_axi_cfg_wm_xbar_reg,
.clear_wm_xbar_reg = msm_vfe44_axi_clear_wm_xbar_reg,
.cfg_ub = msm_vfe44_cfg_axi_ub,
.cfg_ub = msm_vfe47_cfg_axi_ub,
.read_wm_ping_pong_addr =
msm_vfe44_read_wm_ping_pong_addr,
.update_ping_pong_addr =
@ -1895,6 +1843,8 @@ struct msm_vfe_hardware_info vfe44_hw_info = {
.restart = msm_vfe44_axi_restart,
.update_cgc_override =
msm_vfe44_axi_update_cgc_override,
.ub_reg_offset = msm_vfe44_ub_reg_offset,
.get_ub_size = msm_vfe44_get_ub_size,
},
.core_ops = {
.reg_update = msm_vfe44_reg_update,

97
drivers/media/platform/msm/camera_v2/isp/msm_isp46.c
View file

@ -88,6 +88,18 @@ static uint8_t stats_pingpong_offset_map[] = {
#define VFE46_CLK_IDX 2
uint32_t msm_vfe46_ub_reg_offset(struct vfe_device *vfe_dev, int wm_idx)
{
return (VFE46_WM_BASE(wm_idx) + 0x10);
}
uint32_t msm_vfe46_get_ub_size(struct vfe_device *vfe_dev)
{
if (vfe_dev->pdev->id == ISP_VFE0)
return MSM_ISP46_TOTAL_IMAGE_UB_VFE0;
return MSM_ISP46_TOTAL_IMAGE_UB_VFE1;
}
static void msm_vfe46_config_irq(struct vfe_device *vfe_dev,
uint32_t irq0_mask, uint32_t irq1_mask,
enum msm_isp_irq_operation oper)
@ -514,7 +526,7 @@ static long msm_vfe46_reset_hardware(struct vfe_device *vfe_dev,
msm_camera_io_w(0xFFFFFEFF, vfe_dev->vfe_base + 0x68);
msm_camera_io_w(0x1, vfe_dev->vfe_base + 0x58);
vfe_dev->hw_info->vfe_ops.axi_ops.
reload_wm(vfe_dev, vfe_dev->vfe_base, 0x0001FFFF);
reload_wm(vfe_dev, vfe_dev->vfe_base, 0x0031FFFF);
}
if (blocking_call) {
@ -1326,85 +1338,6 @@ static void msm_vfe46_axi_clear_wm_xbar_reg(
vfe_dev->vfe_base + VFE46_XBAR_BASE(wm));
}
static void msm_vfe46_cfg_axi_ub_equal_default(
struct vfe_device *vfe_dev)
{
int i;
uint32_t ub_offset = 0;
struct msm_vfe_axi_shared_data *axi_data =
&vfe_dev->axi_data;
uint32_t total_image_size = 0;
uint8_t num_used_wms = 0;
uint32_t prop_size = 0;
uint32_t wm_ub_size;
uint64_t delta;
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
if (axi_data->free_wm[i] > 0) {
num_used_wms++;
total_image_size += axi_data->wm_image_size[i];
}
}
if (vfe_dev->pdev->id == ISP_VFE0) {
prop_size = MSM_ISP46_TOTAL_IMAGE_UB_VFE0 -
axi_data->hw_info->min_wm_ub * num_used_wms;
} else if (vfe_dev->pdev->id == ISP_VFE1) {
prop_size = MSM_ISP46_TOTAL_IMAGE_UB_VFE1 -
axi_data->hw_info->min_wm_ub * num_used_wms;
} else {
pr_err("%s: incorrect VFE device\n", __func__);
}
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
if (axi_data->free_wm[i]) {
delta = (uint64_t)axi_data->wm_image_size[i] *
(uint64_t)prop_size;
do_div(delta, total_image_size);
wm_ub_size = axi_data->hw_info->min_wm_ub +
(uint32_t)delta;
msm_camera_io_w(ub_offset << 16 | (wm_ub_size - 1),
vfe_dev->vfe_base + VFE46_WM_BASE(i) + 0x10);
ub_offset += wm_ub_size;
} else
msm_camera_io_w(0,
vfe_dev->vfe_base + VFE46_WM_BASE(i) + 0x10);
}
}
static void msm_vfe46_cfg_axi_ub_equal_slicing(
struct vfe_device *vfe_dev)
{
int i;
uint32_t ub_offset = 0;
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
uint32_t ub_equal_slice = 0;
if (vfe_dev->pdev->id == ISP_VFE0) {
ub_equal_slice = MSM_ISP46_TOTAL_IMAGE_UB_VFE0 /
axi_data->hw_info->num_wm;
} else if (vfe_dev->pdev->id == ISP_VFE1) {
ub_equal_slice = MSM_ISP46_TOTAL_IMAGE_UB_VFE1 /
axi_data->hw_info->num_wm;
} else {
pr_err("%s: incorrect VFE device\n ", __func__);
}
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
msm_camera_io_w(ub_offset << 16 | (ub_equal_slice - 1),
vfe_dev->vfe_base + VFE46_WM_BASE(i) + 0x10);
ub_offset += ub_equal_slice;
}
}
static void msm_vfe46_cfg_axi_ub(struct vfe_device *vfe_dev)
{
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
axi_data->wm_ub_cfg_policy = MSM_WM_UB_CFG_DEFAULT;
if (axi_data->wm_ub_cfg_policy == MSM_WM_UB_EQUAL_SLICING)
msm_vfe46_cfg_axi_ub_equal_slicing(vfe_dev);
else
msm_vfe46_cfg_axi_ub_equal_default(vfe_dev);
}
static void msm_vfe46_read_wm_ping_pong_addr(
struct vfe_device *vfe_dev)
{
@ -1974,7 +1907,7 @@ struct msm_vfe_hardware_info vfe46_hw_info = {
.clear_wm_reg = msm_vfe46_axi_clear_wm_reg,
.cfg_wm_xbar_reg = msm_vfe46_axi_cfg_wm_xbar_reg,
.clear_wm_xbar_reg = msm_vfe46_axi_clear_wm_xbar_reg,
.cfg_ub = msm_vfe46_cfg_axi_ub,
.cfg_ub = msm_vfe47_cfg_axi_ub,
.read_wm_ping_pong_addr =
msm_vfe46_read_wm_ping_pong_addr,
.update_ping_pong_addr =
@ -1986,6 +1919,8 @@ struct msm_vfe_hardware_info vfe46_hw_info = {
.restart = msm_vfe46_axi_restart,
.update_cgc_override =
msm_vfe46_axi_update_cgc_override,
.ub_reg_offset = msm_vfe46_ub_reg_offset,
.get_ub_size = msm_vfe46_get_ub_size,
},
.core_ops = {
.reg_update = msm_vfe46_reg_update,

136
drivers/media/platform/msm/camera_v2/isp/msm_isp47.c
View file

@ -148,6 +148,18 @@ static struct msm_bus_scale_pdata msm_isp_bus_client_pdata = {
.name = "msm_camera_isp",
};
uint32_t msm_vfe47_ub_reg_offset(struct vfe_device *vfe_dev, int wm_idx)
{
return (VFE47_WM_BASE(wm_idx) + 0x18);
}
uint32_t msm_vfe47_get_ub_size(struct vfe_device *vfe_dev)
{
if (vfe_dev->pdev->id == ISP_VFE0)
return MSM_ISP47_TOTAL_IMAGE_UB_VFE0;
return MSM_ISP47_TOTAL_IMAGE_UB_VFE1;
}
void msm_vfe47_config_irq(struct vfe_device *vfe_dev,
uint32_t irq0_mask, uint32_t irq1_mask,
enum msm_isp_irq_operation oper)
@ -600,10 +612,14 @@ void msm_vfe47_process_reg_update(struct vfe_device *vfe_dev,
MSM_ISP_COMP_IRQ_REG_UPD);
msm_isp_process_reg_upd_epoch_irq(vfe_dev, i,
MSM_ISP_COMP_IRQ_REG_UPD, ts);
/* if 0 streams then force reg update */
if (vfe_dev->axi_data.src_info
[i].stream_count == 0 &&
vfe_dev->axi_data.src_info[i].active)
/*
* if only camif raw streams active then force
* reg update
*/
if (vfe_dev->axi_data.src_info[VFE_PIX_0].
raw_stream_count > 0 &&
vfe_dev->axi_data.src_info[VFE_PIX_0].
stream_count == 0)
vfe_dev->hw_info->vfe_ops.core_ops.
reg_update(vfe_dev, i);
break;
@ -739,7 +755,7 @@ long msm_vfe47_reset_hardware(struct vfe_device *vfe_dev,
msm_camera_io_w(0xFFFFFEFF, vfe_dev->vfe_base + 0x68);
msm_camera_io_w(0x1, vfe_dev->vfe_base + 0x58);
vfe_dev->hw_info->vfe_ops.axi_ops.
reload_wm(vfe_dev, vfe_dev->vfe_base, 0x0001FFFF);
reload_wm(vfe_dev, vfe_dev->vfe_base, 0x0031FFFF);
}
if (blocking_call) {
@ -1717,7 +1733,8 @@ void msm_vfe47_axi_clear_wm_xbar_reg(
void msm_vfe47_cfg_axi_ub_equal_default(
struct vfe_device *vfe_dev)
struct vfe_device *vfe_dev,
enum msm_vfe_input_src frame_src)
{
int i;
uint32_t ub_offset = 0;
@ -1729,34 +1746,75 @@ void msm_vfe47_cfg_axi_ub_equal_default(
uint32_t wm_ub_size;
uint64_t delta;
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
if (axi_data->free_wm[i] > 0) {
num_used_wms++;
total_image_size += axi_data->wm_image_size[i];
if (frame_src == VFE_PIX_0) {
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
if (axi_data->free_wm[i] &&
SRC_TO_INTF(
HANDLE_TO_IDX(axi_data->free_wm[i])) ==
VFE_PIX_0) {
num_used_wms++;
total_image_size +=
axi_data->wm_image_size[i];
}
}
ub_offset = (axi_data->hw_info->num_rdi * 2) *
axi_data->hw_info->min_wm_ub;
prop_size = vfe_dev->hw_info->vfe_ops.axi_ops.
get_ub_size(vfe_dev) -
axi_data->hw_info->min_wm_ub * (num_used_wms +
axi_data->hw_info->num_rdi * 2);
}
if (vfe_dev->pdev->id == ISP_VFE0) {
prop_size = MSM_ISP47_TOTAL_IMAGE_UB_VFE0 -
axi_data->hw_info->min_wm_ub * num_used_wms;
} else if (vfe_dev->pdev->id == ISP_VFE1) {
prop_size = MSM_ISP47_TOTAL_IMAGE_UB_VFE1 -
axi_data->hw_info->min_wm_ub * num_used_wms;
} else {
pr_err("%s: incorrect VFE device\n", __func__);
}
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
if (axi_data->free_wm[i]) {
if (!axi_data->free_wm[i]) {
msm_camera_io_w(0,
vfe_dev->vfe_base +
vfe_dev->hw_info->vfe_ops.axi_ops.
ub_reg_offset(vfe_dev, i));
continue;
}
if (frame_src != SRC_TO_INTF(
HANDLE_TO_IDX(axi_data->free_wm[i])))
continue;
if (frame_src == VFE_PIX_0) {
delta = (uint64_t)axi_data->wm_image_size[i] *
(uint64_t)prop_size;
do_div(delta, total_image_size);
wm_ub_size = axi_data->hw_info->min_wm_ub +
(uint64_t)prop_size;
do_div(delta, total_image_size);
wm_ub_size = axi_data->hw_info->min_wm_ub +
(uint32_t)delta;
msm_camera_io_w(ub_offset << 16 | (wm_ub_size - 1),
vfe_dev->vfe_base + VFE47_WM_BASE(i) + 0x18);
vfe_dev->vfe_base +
vfe_dev->hw_info->vfe_ops.axi_ops.
ub_reg_offset(vfe_dev, i));
ub_offset += wm_ub_size;
} else
msm_camera_io_w(0,
vfe_dev->vfe_base + VFE47_WM_BASE(i) + 0x18);
} else {
uint32_t rdi_ub_offset;
int plane;
int vfe_idx;
struct msm_vfe_axi_stream *stream_info;
stream_info = msm_isp_get_stream_common_data(vfe_dev,
HANDLE_TO_IDX(axi_data->free_wm[i]));
vfe_idx = msm_isp_get_vfe_idx_for_stream(vfe_dev,
stream_info);
for (plane = 0; plane < stream_info->num_planes;
plane++)
if (stream_info->wm[vfe_idx][plane] ==
axi_data->free_wm[i])
break;
rdi_ub_offset = ((SRC_TO_INTF(
HANDLE_TO_IDX(axi_data->free_wm[i])) -
VFE_RAW_0 * 2) + plane) *
axi_data->hw_info->min_wm_ub;
wm_ub_size = axi_data->hw_info->min_wm_ub * 2;
msm_camera_io_w(rdi_ub_offset << 16 | (wm_ub_size - 1),
vfe_dev->vfe_base +
vfe_dev->hw_info->vfe_ops.axi_ops.
ub_reg_offset(vfe_dev, i));
}
}
}
@ -1767,23 +1825,21 @@ void msm_vfe47_cfg_axi_ub_equal_slicing(
uint32_t ub_offset = 0;
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
uint32_t ub_equal_slice = 0;
if (vfe_dev->pdev->id == ISP_VFE0) {
ub_equal_slice = MSM_ISP47_TOTAL_IMAGE_UB_VFE0 /
axi_data->hw_info->num_wm;
} else if (vfe_dev->pdev->id == ISP_VFE1) {
ub_equal_slice = MSM_ISP47_TOTAL_IMAGE_UB_VFE1 /
axi_data->hw_info->num_wm;
} else {
pr_err("%s: incorrect VFE device\n ", __func__);
}
ub_equal_slice = vfe_dev->hw_info->vfe_ops.axi_ops.
get_ub_size(vfe_dev) /
axi_data->hw_info->num_wm;
for (i = 0; i < axi_data->hw_info->num_wm; i++) {
msm_camera_io_w(ub_offset << 16 | (ub_equal_slice - 1),
vfe_dev->vfe_base + VFE47_WM_BASE(i) + 0x18);
vfe_dev->vfe_base +
vfe_dev->hw_info->vfe_ops.axi_ops.
ub_reg_offset(vfe_dev, i));
ub_offset += ub_equal_slice;
}
}
void msm_vfe47_cfg_axi_ub(struct vfe_device *vfe_dev)
void msm_vfe47_cfg_axi_ub(struct vfe_device *vfe_dev,
enum msm_vfe_input_src frame_src)
{
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
@ -1791,7 +1847,7 @@ void msm_vfe47_cfg_axi_ub(struct vfe_device *vfe_dev)
if (axi_data->wm_ub_cfg_policy == MSM_WM_UB_EQUAL_SLICING)
msm_vfe47_cfg_axi_ub_equal_slicing(vfe_dev);
else
msm_vfe47_cfg_axi_ub_equal_default(vfe_dev);
msm_vfe47_cfg_axi_ub_equal_default(vfe_dev, frame_src);
}
void msm_vfe47_read_wm_ping_pong_addr(
@ -2774,6 +2830,8 @@ struct msm_vfe_hardware_info vfe47_hw_info = {
.restart = msm_vfe47_axi_restart,
.update_cgc_override =
msm_vfe47_axi_update_cgc_override,
.ub_reg_offset = msm_vfe47_ub_reg_offset,
.get_ub_size = msm_vfe47_get_ub_size,
},
.core_ops = {
.reg_update = msm_vfe47_reg_update,

8
drivers/media/platform/msm/camera_v2/isp/msm_isp47.h
View file

@ -97,10 +97,12 @@ void msm_vfe47_axi_clear_wm_xbar_reg(
struct vfe_device *vfe_dev,
struct msm_vfe_axi_stream *stream_info, uint8_t plane_idx);
void msm_vfe47_cfg_axi_ub_equal_default(
struct vfe_device *vfe_dev);
struct vfe_device *vfe_dev,
enum msm_vfe_input_src frame_src);
void msm_vfe47_cfg_axi_ub_equal_slicing(
struct vfe_device *vfe_dev);
void msm_vfe47_cfg_axi_ub(struct vfe_device *vfe_dev);
void msm_vfe47_cfg_axi_ub(struct vfe_device *vfe_dev,
enum msm_vfe_input_src frame_src);
void msm_vfe47_read_wm_ping_pong_addr(
struct vfe_device *vfe_dev);
void msm_vfe47_update_ping_pong_addr(
@ -198,4 +200,6 @@ void msm_vfe47_config_irq(struct vfe_device *vfe_dev,
int msm_isp47_ahb_clk_cfg(struct vfe_device *vfe_dev,
struct msm_isp_ahb_clk_cfg *ahb_cfg);
void msm_vfe47_set_halt_restart_mask(struct vfe_device *vfe_dev);
uint32_t msm_vfe47_ub_reg_offset(struct vfe_device *vfe_dev, int wm_idx);
uint32_t msm_vfe47_get_ub_size(struct vfe_device *vfe_dev);
#endif /* __MSM_ISP47_H__ */

2
drivers/media/platform/msm/camera_v2/isp/msm_isp48.c
View file

@ -287,6 +287,8 @@ struct msm_vfe_hardware_info vfe48_hw_info = {
.restart = msm_vfe47_axi_restart,
.update_cgc_override =
msm_vfe47_axi_update_cgc_override,
.ub_reg_offset = msm_vfe47_ub_reg_offset,
.get_ub_size = msm_vfe47_get_ub_size,
},
.core_ops = {
.reg_update = msm_vfe47_reg_update,

100
drivers/media/platform/msm/camera_v2/isp/msm_isp_axi_util.c
View file

@ -700,7 +700,7 @@ void msm_isp_check_for_output_error(struct vfe_device *vfe_dev,
sof_info->regs_not_updated =
vfe_dev->reg_update_requested;
}
for (i = 0; i < VFE_AXI_SRC_MAX; i++) {
for (i = 0; i < RDI_INTF_0; i++) {
stream_info = msm_isp_get_stream_common_data(vfe_dev,
i);
stream_idx = HANDLE_TO_IDX(stream_info->stream_handle[0]);
@ -980,16 +980,12 @@ void msm_isp_notify(struct vfe_device *vfe_dev, uint32_t event_type,
event_data.u.sof_info.ms_delta_info.
num_delta_info = 1;
}
spin_unlock_irqrestore(&vfe_dev->common_data->
common_dev_data_lock, flags);
} else {
spin_unlock_irqrestore(&vfe_dev->common_data->
common_dev_data_lock, flags);
if (frame_src <= VFE_RAW_2) {
msm_isp_check_for_output_error(vfe_dev, ts,
&event_data.u.sof_info);
}
}
spin_unlock_irqrestore(&vfe_dev->common_data->
common_dev_data_lock, flags);
if (frame_src == VFE_PIX_0)
msm_isp_check_for_output_error(vfe_dev, ts,
&event_data.u.sof_info);
break;
default:
@ -2114,19 +2110,19 @@ int msm_isp_drop_frame(struct vfe_device *vfe_dev,
*
* If stream count on an input line is 0 then disable the input
*/
static void msm_isp_input_disable(struct vfe_device *vfe_dev)
static void msm_isp_input_disable(struct vfe_device *vfe_dev, int cmd_type)
{
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev->axi_data;
int ext_read =
(axi_data->src_info[VFE_PIX_0].input_mux == EXTERNAL_READ);
int stream_count;
int total_stream_count = 0;
int i;
struct msm_vfe_src_info *src_info;
int ext_read =
(axi_data->src_info[VFE_PIX_0].input_mux == EXTERNAL_READ);
for (i = 0; i < VFE_SRC_MAX; i++)
total_stream_count += axi_data->src_info[i].stream_count +
axi_data->src_info[i].raw_stream_count;
axi_data->src_info[i].raw_stream_count;
for (i = 0; i < VFE_SRC_MAX; i++) {
stream_count = axi_data->src_info[i].stream_count +
@ -2168,20 +2164,21 @@ static void msm_isp_input_disable(struct vfe_device *vfe_dev)
&vfe_dev->common_data->common_dev_data_lock,
flags);
}
if (i != VFE_PIX_0 || ext_read)
continue;
/* halt camif */
if (total_stream_count == 0) {
if (total_stream_count == 0 || cmd_type == STOP_IMMEDIATELY)
vfe_dev->hw_info->vfe_ops.core_ops.
update_camif_state(vfe_dev,
DISABLE_CAMIF_IMMEDIATELY);
} else {
else
vfe_dev->hw_info->vfe_ops.core_ops.
update_camif_state(vfe_dev, DISABLE_CAMIF);
}
update_camif_state(vfe_dev,
DISABLE_CAMIF);
}
/* halt and reset hardware if all streams are disabled */
/*
* halt and reset hardware if all streams are disabled, in this case
* ispif is halted immediately as well
*/
if (total_stream_count == 0) {
vfe_dev->hw_info->vfe_ops.axi_ops.halt(vfe_dev, 1);
msm_isp_flush_tasklet(vfe_dev);
@ -2231,6 +2228,10 @@ static void msm_isp_input_enable(struct vfe_device *vfe_dev,
axi_data->src_info[i].frame_id =
axi_data->src_info[VFE_PIX_0].frame_id;
}
/* when start reset overflow state and cfg ub for this intf */
vfe_dev->hw_info->vfe_ops.axi_ops.cfg_ub(vfe_dev, i);
atomic_set(&vfe_dev->error_info.overflow_state,
NO_OVERFLOW);
if (i != VFE_PIX_0 || ext_read)
continue;
/* for camif input the camif needs enabling */
@ -2335,15 +2336,22 @@ static int msm_isp_init_stream_ping_pong_reg(
/* Set address for both PING & PO NG register */
rc = msm_isp_cfg_ping_pong_address(
stream_info, VFE_PING_FLAG);
/* No buffer available on start is not error */
if (rc == -ENOMEM && stream_info->stream_type != BURST_STREAM)
return 0;
if (rc < 0) {
pr_err("%s: No free buffer for ping\n",
__func__);
return rc;
}
if (stream_info->stream_type != BURST_STREAM ||
stream_info->runtime_num_burst_capture > 1)
stream_info->runtime_num_burst_capture > 1) {
rc = msm_isp_cfg_ping_pong_address(
stream_info, VFE_PONG_FLAG);
/* No buffer available on start is not error */
if (rc == -ENOMEM)
return 0;
}
if (rc < 0) {
pr_err("%s: No free buffer for pong\n",
@ -2690,7 +2698,6 @@ static void __msm_isp_stop_axi_streams(struct vfe_device *vfe_dev,
int i;
struct msm_vfe_axi_shared_data *axi_data;
struct msm_isp_timestamp timestamp;
int total_stream_count = 0;
uint32_t bufq_id = 0, bufq_handle = 0;
struct msm_vfe_axi_stream *stream_info;
unsigned long flags;
@ -2712,7 +2719,7 @@ static void __msm_isp_stop_axi_streams(struct vfe_device *vfe_dev,
for (k = 0; k < MAX_VFE; k++) {
if (!update_vfes[k])
continue;
msm_isp_input_disable(update_vfes[k]);
msm_isp_input_disable(update_vfes[k], cmd_type);
}
for (i = 0; i < num_streams; i++) {
@ -2748,44 +2755,28 @@ static void __msm_isp_stop_axi_streams(struct vfe_device *vfe_dev,
}
for (k = 0; k < MAX_VFE; k++) {
int ext_read;
if (!update_vfes[k])
continue;
vfe_dev = update_vfes[k];
axi_data = &vfe_dev->axi_data;
ext_read =
(axi_data->src_info[VFE_PIX_0].input_mux == EXTERNAL_READ);
for (i = 0; i < VFE_SRC_MAX; i++) {
total_stream_count +=
axi_data->src_info[i].stream_count +
axi_data->src_info[i].raw_stream_count;
if (i != VFE_PIX_0)
continue;
if (axi_data->src_info[i].stream_count == 0) {
vfe_dev->hw_info->vfe_ops.stats_ops.
enable_module(vfe_dev, 0xFF, 0);
/* reg update for PIX with 0 streams active */
if (ext_read == 0)
vfe_dev->hw_info->vfe_ops.core_ops.
reg_update(vfe_dev, VFE_PIX_0);
}
if (axi_data->src_info[VFE_PIX_0].active == 0) {
vfe_dev->hw_info->vfe_ops.stats_ops.enable_module(
vfe_dev, 0xFF, 0);
}
}
for (i = 0; i < num_streams; i++) {
stream_info = streams[i];
spin_lock_irqsave(&stream_info->lock, flags);
intf = SRC_TO_INTF(stream_info->stream_src);
if (total_stream_count == 0 ||
((stream_info->stream_type == BURST_STREAM) &&
stream_info->runtime_num_burst_capture == 0)) {
spin_lock_irqsave(&stream_info->lock, flags);
if (((stream_info->stream_type == BURST_STREAM) &&
stream_info->runtime_num_burst_capture == 0) ||
(stream_info->vfe_dev[0]->axi_data.src_info[intf].
active == 0)) {
while (stream_info->state != INACTIVE)
__msm_isp_axi_stream_update(
stream_info, &timestamp);
spin_unlock_irqrestore(&stream_info->lock, flags);
continue;
}
spin_unlock_irqrestore(&stream_info->lock, flags);
}
rc = msm_isp_axi_wait_for_streams(streams, num_streams, 0);
@ -2868,7 +2859,6 @@ static int msm_isp_start_axi_stream(struct vfe_device *vfe_dev_ioctl,
struct msm_isp_timestamp timestamp;
struct vfe_device *update_vfes[MAX_VFE] = {0, 0};
int k;
uint32_t num_active_streams[MAX_VFE] = {0, 0};
struct vfe_device *vfe_dev;
struct msm_vfe_axi_shared_data *axi_data = &vfe_dev_ioctl->axi_data;
@ -2914,9 +2904,6 @@ static int msm_isp_start_axi_stream(struct vfe_device *vfe_dev_ioctl,
continue;
update_vfes[stream_info->vfe_dev[k]->pdev->id] =
stream_info->vfe_dev[k];
num_active_streams[stream_info->vfe_dev[k]->pdev->id] =
stream_info->vfe_dev[k]->axi_data.
num_active_stream;
}
msm_isp_reset_framedrop(vfe_dev_ioctl, stream_info);
rc = msm_isp_init_stream_ping_pong_reg(stream_info);
@ -2976,13 +2963,6 @@ static int msm_isp_start_axi_stream(struct vfe_device *vfe_dev_ioctl,
vfe_dev = update_vfes[i];
if (!vfe_dev)
continue;
if (num_active_streams[i] == 0) {
/* Configure UB */
vfe_dev->hw_info->vfe_ops.axi_ops.cfg_ub(vfe_dev);
/* when start reset overflow state */
atomic_set(&vfe_dev->error_info.overflow_state,
NO_OVERFLOW);
}
msm_isp_update_stream_bandwidth(vfe_dev);
vfe_dev->hw_info->vfe_ops.axi_ops.reload_wm(vfe_dev,
vfe_dev->vfe_base, wm_reload_mask[i]);

26
drivers/media/platform/msm/camera_v2/isp/msm_isp_stats_util.c
View file

@ -848,7 +848,6 @@ int msm_isp_stats_reset(struct vfe_device *vfe_dev)
struct msm_vfe_stats_stream *stream_info = NULL;
struct msm_isp_timestamp timestamp;
unsigned long flags;
int k;
msm_isp_get_timestamp(&timestamp, vfe_dev);
@ -877,15 +876,6 @@ int msm_isp_stats_reset(struct vfe_device *vfe_dev)
ISP_EVENT_BUF_FATAL_ERROR);
return rc;
}
for (k = 0; k < stream_info->num_isp; k++) {
struct vfe_device *temp_vfe_dev =
stream_info->vfe_dev[k];
temp_vfe_dev->hw_info->vfe_ops.stats_ops.
cfg_wm_irq_mask(
temp_vfe_dev, stream_info);
temp_vfe_dev->hw_info->vfe_ops.stats_ops.enable_module(
temp_vfe_dev, BIT(i), 1);
}
}
return rc;
@ -912,6 +902,22 @@ int msm_isp_stats_restart(struct vfe_device *vfe_dev)
stream_info->composite_irq[j] = 0;
msm_isp_init_stats_ping_pong_reg(
stream_info);
for (j = 0; j < stream_info->num_isp; j++) {
struct vfe_device *temp_vfe_dev =
stream_info->vfe_dev[j];
uint8_t comp_flag = stream_info->composite_flag;
temp_vfe_dev->hw_info->vfe_ops.stats_ops.enable_module(
temp_vfe_dev, BIT(i), 1);
if (comp_flag)
temp_vfe_dev->hw_info->vfe_ops.stats_ops.
cfg_comp_mask(temp_vfe_dev, BIT(i),
(comp_flag - 1), 1);
else
temp_vfe_dev->hw_info->vfe_ops.stats_ops.
cfg_wm_irq_mask(
temp_vfe_dev, stream_info);
}
spin_unlock_irqrestore(&stream_info->lock, flags);
}