From fef7d8cbacf948e0e85a4952b1fbe98f1e88e073 Mon Sep 17 00:00:00 2001 From: David Collins Date: Mon, 18 Jan 2016 18:18:24 -0800 Subject: [PATCH] ARM: dts: msm: add the CPU frequency plan for msm8996pro Update the frequency plan for the MSM8996pro CPU clocks. Change-Id: Ib395678da8be33ff30a3630837008ee911bc5616 Signed-off-by: David Collins --- arch/arm/boot/dts/qcom/msm8996pro.dtsi | 141 +++++++++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/arch/arm/boot/dts/qcom/msm8996pro.dtsi b/arch/arm/boot/dts/qcom/msm8996pro.dtsi index 23d28adc355b..a5598766641e 100644 --- a/arch/arm/boot/dts/qcom/msm8996pro.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996pro.dtsi @@ -525,3 +525,144 @@ qcom,cpr-aging-ro-scaling-factor = <2950>; qcom,allow-aging-voltage-adjustment = <1>; }; + +&clock_cpu { + compatible = "qcom,cpu-clock-8996-v3"; + qcom,pwrcl-speedbin0-v0 = + < 0 0 >, + < 307200000 1 >, + < 384000000 2 >, + < 460800000 3 >, + < 537600000 4 >, + < 614400000 5 >, + < 691200000 6 >, + < 768000000 7 >, + < 844800000 8 >, + < 902400000 9 >, + < 979200000 10 >, + < 1056000000 11 >, + < 1132800000 12 >, + < 1209600000 13 >, + < 1286400000 14 >, + < 1363200000 15 >, + < 1440000000 16 >, + < 1516800000 17 >, + < 1593600000 18 >; + qcom,pwrcl-speedbin1-v0 = + < 0 0 >, + < 307200000 1 >, + < 384000000 2 >, + < 460800000 3 >, + < 537600000 4 >, + < 614400000 5 >, + < 691200000 6 >, + < 768000000 7 >, + < 844800000 8 >, + < 902400000 9 >, + < 979200000 10 >, + < 1056000000 11 >, + < 1132800000 12 >, + < 1209600000 13 >, + < 1286400000 14 >, + < 1363200000 15 >, + < 1440000000 16 >, + < 1516800000 17 >, + < 1593600000 18 >; + qcom,perfcl-speedbin0-v0 = + < 0 0 >, + < 307200000 1 >, + < 384000000 2 >, + < 460800000 3 >, + < 537600000 4 >, + < 614400000 5 >, + < 691200000 6 >, + < 748800000 7 >, + < 825600000 8 >, + < 902400000 9 >, + < 979200000 10 >, + < 1056000000 11 >, + < 1132800000 12 >, + < 1209600000 13 >, + < 1286400000 14 >, + < 1363200000 15 >, + < 1440000000 16 >, + < 1516800000 17 >, + < 1593600000 18 >, + < 1670400000 19 >, + < 1747200000 20 >, + < 1824000000 21 >, + < 1900800000 22 >, + < 1977600000 23 >, + < 2054400000 24 >, + < 2150400000 25 >; + /* Additional frequencies to be added after characterization. */ + qcom,perfcl-speedbin1-v0 = + < 0 0 >, + < 307200000 1 >, + < 384000000 2 >, + < 460800000 3 >, + < 537600000 4 >, + < 614400000 5 >, + < 691200000 6 >, + < 748800000 7 >, + < 825600000 8 >, + < 902400000 9 >, + < 979200000 10 >, + < 1056000000 11 >, + < 1132800000 12 >, + < 1209600000 13 >, + < 1286400000 14 >, + < 1363200000 15 >, + < 1440000000 16 >, + < 1516800000 17 >, + < 1593600000 18 >, + < 1670400000 19 >, + < 1747200000 20 >, + < 1824000000 21 >, + < 1900800000 22 >, + < 1977600000 23 >, + < 2054400000 24 >, + < 2150400000 25 >; + qcom,cbf-speedbin0-v0 = + < 0 0 >, + < 192000000 1 >, + < 307200000 2 >, + < 384000000 3 >, + < 441600000 4 >, + < 537600000 5 >, + < 614400000 6 >, + < 691200000 7 >, + < 768000000 8 >, + < 844800000 9 >, + < 902400000 10 >, + < 979200000 11 >, + < 1056000000 12 >, + < 1132800000 13 >, + < 1190400000 14 >, + < 1286400000 15 >, + < 1363200000 16 >, + < 1440000000 17 >, + < 1516800000 18 >, + < 1593600000 19 >; + qcom,cbf-speedbin1-v0 = + < 0 0 >, + < 192000000 1 >, + < 307200000 2 >, + < 384000000 3 >, + < 441600000 4 >, + < 537600000 5 >, + < 614400000 6 >, + < 691200000 7 >, + < 768000000 8 >, + < 844800000 9 >, + < 902400000 10 >, + < 979200000 11 >, + < 1056000000 12 >, + < 1132800000 13 >, + < 1190400000 14 >, + < 1286400000 15 >, + < 1363200000 16 >, + < 1440000000 17 >, + < 1516800000 18 >, + < 1593600000 19 >; +};